Chip gallery


 





L. Lin, S. Jain, M. Alioto, “Reconfigurable Clock Networks for Random Skew Mitigation from Subthreshold to Nominal Voltage,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 440-441



 
PUF chip (2014)



A. Alvarez, W. Zhao, M. Alioto, “15-fJ/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra/Inter PUF Hamming Distance Separation in 65nm,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 258-259