Chip gallery


 2018




(under publication)


2017


First sub-mW feature extraction engine for distributed computer vision


An energy-quality scalable (EQSCALE) feature extraction accelerator for IoT vision applications is presented. Knobs are introduced to dynamically adjust the tradeoff between energy and feature extraction quality, leveraging the intrinsic redundancy in video frames and the robustness of object recognition against missing features. The active area of the accelerator is 0.55mm2. EQSCALE enables at least 5.7X energy improvement and 1.8X area reduction over state-of-the-art accelerators. To the best of our knowledge, EQSCALE is the first feature extraction accelerator operating in the sub-mW range (0.51mW at VGA resolution and 30 fps, and 0.19mW at 5 fps).

 
 2017


Fully-Synthesizable C-Element Based PUF Featuring Temperature Variation Compensation with Native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm

A fully-synthesizable Physically Unclonable Function (PUF) with hysteresis-enhanced stability and active compensation of temperature variations is proposed. To reduce undesired bit flips, hysteretic behavior is obtained through the insertion of a Muller C-element output stage. A feedback scheme is also introduced to compensate the effect of temperature variations at run time. Native worst-case BER of 2.8% is measured under 0.8-1.0V and 25-85°C, with instability degradation with temperature being 0.15% per 10°C. The PUF bitcell consumes 1.02fJ/b at 0.9V. This PUF can be designed with fully automated standard cell-based flows, thus enabling substantial design effort reduction compared to prior art based on custom design styles.



 2017



FFT engine with reconfigurable microarchitecture down to the pipestage level for wide energy/voltage scaling

Dynamically adaptable pipelines with its full integration with automated digital flows at design time and with dynamic voltage scaling schemes at run time is demonstrated with a 256-point radix-4 fixed-point FFT engine on a 40-nm test chip. Measurements show energy savings up to 30% (38%) at iso throughput (iso-voltage). Area and worst-case performance penalty are 5% and 11%, respectively.


 2017


First demonstration of reconfigurable clock networks for adaptation under wide voltage scaling

A reconfigurable clock network design for operation from sub-threshold to nominal voltage is presented. The number of levels is adjusted with more levels at nominal voltage to mitigate the impact of wire delay, and fewer in sub-threshold to mitigate the dominant random skew due to repeaters. Clock skew is reduced by up to 2.5 standard deviations and enables 110mV Vmin reduction at 1.8% area penalty in an FFT 40nm testchip, compared to traditional clock networks.


2015 
PUF chip (2014)




15-fJ/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra/Inter PUF Hamming Distance Separation in 65nm

A static class of Physically Unclonable Functions for secure key generation and chip identification is presented. Energy down to 15 fJ/bit is achieved, key reproducibility and uniqueness meet inter/intra-PUF Hamming distance separation of 140X or greater, randomness passes all NIST tests. Native unstable bits are less than 2% at nominal conditions and less than 5% in 0.7-1 V voltage and 25-85 oC temperature range, before applying any further post-silicon technique for stability enhancement.