Research Programme in Energy-autonomous always-on cognitive and attentive cameras for distributed real-time vision with milliwatt power consumption
Publications
1 S. Jain, L. Lin, M. Alioto, Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling, Springer, 2020 2 S. Jain, L. Longyang, M. Alioto, “Automated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling,” accepted to IEEE Trans. on VLSI Systems 3 O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation,” accepted to IEEE Access 4 A. Alvarez, G. Ponnusamy, M. Alioto, “A Sub-mW, Sub-mm2 Energy-Quality Scalable Feature Extraction Accelerator for Distributed Vision in 40nm,” accepted to IEEE Access 5 L. Lin, S. Jain, M. Alioto, “Sub-nW Microcontroller with Dual-Mode Logic and Self-startup for Battery-Indifferent Sensor Nodes,” submitted to IEEE JSSC
1 | S. Jain, L. Lin, M. Alioto, Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling, Springer, 2020 |
2 | S. Jain, L. Longyang, M. Alioto, “Automated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling,” accepted to IEEE Trans. on VLSI Systems |
3 | O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation,” accepted to IEEE Access |
4 | A. Alvarez, G. Ponnusamy, M. Alioto, “A Sub-mW, Sub-mm2 Energy-Quality Scalable Feature Extraction Accelerator for Distributed Vision in 40nm,” accepted to IEEE Access |
5 | L. Lin, S. Jain, M. Alioto, “Sub-nW Microcontroller with Dual-Mode Logic and Self-startup for Battery-Indifferent Sensor Nodes,” submitted to IEEE JSSC |
Presentations
1 | Neural Epitome Search for Architecture-Agnostic Network Compression, International Conference on Learning Representations |
2 | S. Jain, L. Lin, M. Alioto, “Broad-Purpose In-Memory Computing for DSP and Machine Learning Workloads Based on Commercial Bitcell,” being submitted to ASSCC 2020 |
3 | J. H. Teo, K. Ali, S. Sarkar, M. Alioto, “Dual-Mode Clock Gating and Comparator Merging for 2.7X Energy/Conversion Reduction in SAR ADCs under Low-Activity Inputs,” being submitted to ASSCC 2020 |
4 | O. Aiello, P. Crovetti, A. Sharma, M. Alioto, “Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort,” accepted to ICECS 2019 |
5 | S. Jain, L. Longyang, M. Alioto, “Low-Overhead Drop-In Techniques to Extend the Energy-Performance Tradeoff in Microcontrollers Beyond VDD Scaling,” in Proc. of ASSCC 2019, pp. 125-129, Macau (China), Nov. 2019 |
Demos and public materials
Talks