Sub-Project 4: Irrelevant activity skipping/EQ-scalable sensemaking circuits/architectures This sub-project focuses on the circuit and
architectural implications on the sensemaking of the three research directions in
Fig. D11. Regarding the
irrelevant activity skipping, the processing elements
in Fig. D17-D21
will be organized both logically (architecture) and physically (floorplan) in a regular fashion that maps the imager
tiles (see sub-project #2) onto the sub-systems that perform
the corresponding computation. To this aim, novel
chip design methodologies pursuing vertical
integration from physical level to architecture
will be developed in this sub-project,
with the goal of assuring data
locality (to limit the large
energy cost of signal distribution) and maximizing
the reuse of memory accesses (to limit the large energy cost of multiple
accesses to the same memory
address). In regard to the
energy-quality scalability,
this novel capability will be introduced in all components of the SoC.
The fundamental vision algorithm
parameters will be evaluated
as primary candidates for being used as energy-quality
knobs, and their impact on energy
and quality will be preliminarily assessed through high-level simulations (e.g., OpenCV [OCP]).
Also, this sub-project
involves the translation of the
expected research results into measurable chip demonstrators of saliency pre-assessment,
feature extraction, novelty assessment, and deep learning in Fig. D17.
These circuits are designed and
tested in two rounds, respectively
for initial validation and further refinement. The very final version of their
design will be integrated in
the final System on Chip (SoC) demonstration, and its characterization will be
again cross-correlated
with the silicon measurements in the two previous versions, evaluating the
effect of
process/voltage/temperature corners and in both a controlled and real-world environment. | 
