Sub-Project 1: System modeling, exploration, integration, demonstration of cognitive/attentive camerasThis sub-project
addresses the system-level
challenges and unifies the efforts of the other sub-projects into a cohesive modelling, design and verification
framework. Regarding the system
modelling, a high-level simulation framework will be
developed and shared among all PIs
to evaluate the functionality,
the performance and the energy efficiency of individual components, as well as their impact at the system level.
Energy per operation will also be modelled using proprietary models, to preliminarily estimate the
benefit of each innovative
technique before performing time-consuming
circuit and architectural design. The same environment will be used to share a
common database of benchmarks for
quantitative assessment, and to perform experiments in a controlled environment shared
by all researchers in the team. Tentatively, the environment will be in OpenCV-Python [OCP] as a compromise between Python’s code readability (as needed in
collaborative efforts) and
availability of OpenCV libraries
(which has also been used by
the PIs to generate some preliminary results). Such environment will
also be used to generate test vectors for chip testing.
This sub-project also covers the system design, integration and demonstration aspects in CogniVision,
once the above preliminary exploration
is performed, and circuit/architectural techniques
are investigated and developed for silicon implementation in other sub-projects. System integration will be first performed as a
System on Board (SoB), assembling the stand-alone
chips that are generated in the various sub-projects for two silicon rounds. The final
demonstration is instead
performed in the form of a single System on Chip (SoC). Accordingly, chip design partitioning and floor plan will be preliminarily performed, and a mixed-signal simulation/verification environment will be developed to verify the
design from behavioral down to gate-level
and some selected circuit
simulations, when designs become available over time for the blocks in the CogniVision
SoC. Also, this sub-project
focuses on the silicon
infrastructure for chip configuration and
testing, based on the CogniVision chip architecture in Fig. D21.
Once verified and taped out, the
CogniVision chip will be fabricated by a commercial
silicon foundry (e.g., GlobalFoundries)
and tested in a real-world environment to assure that the ultimate quantitative
targets in Table IV are achieved.The targeted use cases in this table are well
within the capabilities of CogniVision, both in
terms of memory (2MBs) and
throughput (<20,000MOPS).The
on-chip microprocessor(tentatively
PULPino by ETHZ, also team
collaborator [PLP]) in Fig. D21 does not affect the performance, as it is only configures the accelerators and weights into the on-chip
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