EditorialsM. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli, Guest Editorial for the Special Issue on Circuits and Systems for the Internet of Things – From Sensing to Sensemaking, in print on IEEE Trans. on Circuits and Systems – part I, Sept. 2017. K. Chakrabarti, M. Alioto, Editorial on the First TVLSI Best AE and Reviewer Awards, IEEE Trans. on VLSI Systems, Aug. 2016. M. Alioto, Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing, IEEE Trans. on Circuits and Systems – part II, vol. 59, no. 12, pp. 849-852, Dec. 2012. Books or book chaptersM. Alioto (Ed.), Enabling the Internet of Things - from Integrated Circuits to Integrated Systems, Springer, 2017.M. Alioto, E. Consoli, G. Palumbo, Flip-Flop Design in Nanometer CMOS - from High Speed to Low Energy, Springer, 2014.M. Alioto, E. Consoli, G. Palumbo, “Design in the Energy-Delay Space,” (Chapter1) in Advanced Circuits for Emerging Technologies, Part I - Digital Design and Power Management, Wiley, March 2012. M. Alioto, G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), New York, Springer, 2005. International journals (2006-today)Q.-K. Trinh, S. Ruocco, M. Alioto, “Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories,” in print on IEEE Trans. on CAS – part I S. Jain, L. Longyang, M. Alioto, “Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures under Wide Voltage Scaling,” IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 632-641, Feb. 2018 R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, “A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/MTJ Circuits,” in print on IEEE Trans. on CAS – part I Q. K. Trinh, S. Ruocco, M. Alioto, “Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs,” IEEE Trans. on CAS – part I, vol. 65, no. 4, pp. 1269-1278, April 2018 Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M Alioto, D. Blaauw, D. Sylvester, “iRazor: Current-Based Error Detection and Correction Scheme for PVT variation in 40-nm ARM Cortex-R4 Processor,” IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 619-631, Feb. 2018 M. Alioto, M. Shahghasemi, “The Internet of Things on Its Edge: Trends towards Its Tipping Point,” in print on the special issue on “Recent Advances on IoT-based Consumer Electronics”, IEEE Consumer Electronics Magazine (invited), vol. 7, no. 1, pp. 77-87, Jan. 2018 S. Jain, L. Lin, M. Alioto, “Design-Oriented Energy Models for Wide Voltage Scaling down to the Minimum Energy Point,” IEEE Trans. on CAS – part I, vol. 64, no. 12, pp. 3115-3125, Dec. 2017 M. Alioto, G. Scotti, A. Trifiletti, “A Novel Framework to Estimate the Path Delay Variability on the Back of an Envelope via the Fan-Out-of-4 Metric,” IEEE Trans. on CAS – part I, vol. 64, no. 8, pp. 2073-2085, Aug. 2017 K. T. Quang, S. Ruocco, M. Alioto, “Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read,” IEEE Trans. on CAS – part I, vol. 63, no. 10, pp. 1652-1660, Oct. 2016 F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “Approximate SRAMs with Dynamic Energy-Quality Management,” IEEE Trans. on VLSI Systems, vol. 24, no. 6, pp. 2128-2141, June 2016 A. Alvarez, W. Zhao, M. Alioto,
“Static Physically Unclonable Functions for Secure Chip Identification with
1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65nm,” IEEE Journal
on Solid-State Circuits, vol. 51, no. 3, pp. 763-775, March 2016 K. T. Quang, S. Ruocco, M. Alioto, “Voltage Scaled STT-MRAMs towards Minimum-Energy Write Access,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 305-318, Sept 2016 F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “SRAM for Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 1310-1323, March 2015 M. Alioto, Elio Consoli, G. Palumbo, “Variations in Nanometer CMOS Flip-Flops: Part II – Energy Variability and Impact of Other Sources of Variations,” IEEE Trans. on CAS – part I, vol. 62, n. 3, pp. 835-843, March 2015 M. Alioto, Elio Consoli, G. Palumbo, “Variations in Nanometer CMOS Flip-Flops: Part I – Impact of Process Variations on Timing,” in print on IEEE Trans. on CAS – part I M. Shoaran, A. Tajalli, M. Alioto, A. Schmid, Y. Leblebici, “Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits,” IEEE Trans. on CAS – part I, vol. 62, no. 2, pp. 458-467, Feb. 2015 L. Freyman, D. Fick, M. Alioto, D. Blaauw, D. Sylvester, “A 346μm2 VCO-based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2462-2473, Nov. 2014 L. Artola, G. Hubert, M. Alioto, “Comparative soft error evaluation of layout cells in FinFET technology,” in print on Microelectronics Reliability (Elsevier) W. Zhao, Y. Ha, M. Alioto, “Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study,” in print on IEEE Trans. on VLSI Systems – available at http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6877700 M. Tache, V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, “Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates” Journal of Low Power Electronics, Vol. 10, N° 1, pp. 137-148, March 2014 (invited, special selection on the 4th European Workshop on CMOS Variability - VARI 2013). M. Alioto, D. Esseni, “Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II – Evaluation at Circuit Level and Design Perspectives,” IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2499-2512, Dec. 2014. D. Esseni, M. Guglielmini, B. Kapidani, T. Rollo, M. Alioto, “Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part I – Device-Circuit Interaction and Evaluation at Device Level,” IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2488-2498, Dec. 2014. E. Consoli, G. Palumbo, J. Rabaey, M. Alioto, “A Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches,” IEEE Trans. on VLSI Systems, vol. 22, no. 7, pp. 1593-1605, July 2014. M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, A. Trifiletti, “Effectiveness of Leakage Power Analysis attacks on DPA-resistant logic styles under process variations,” IEEE Trans. on Circuits and Systems – part I, vol. 61, no. 2, pp. 429-442, Feb. 2014. M. Alioto, E. Consoli, J. Rabaey, ““EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions,” IEEE Journal of Solid-State Circuits ( invited), vol. 48, no. 8, pp. 1921-1932, Aug. 2013.F. Crupi, D. Albano, M. Alioto, J. Franco, L. Selmi, J. Mitard, G. Groeseneken, “Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits,” IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 972-977, March 2013. F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, G. Groeseneken, “Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements,” IEEE Trans. on Circuits and Systems – part II, vol. 59, no. 7, pp. 439-442, July 2012. M. Alioto, G. Palumbo, M. Pennisi, “A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates,” IEEE Trans. on Circuits and Systems – part I, vol. 59, no. 10, pp. 2292-2300, Oct. 2012. F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling,” IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1487-1495, Aug. 2012. D. Baccarin, D. Esseni, M. Alioto, “Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks,” IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1467-1472, Aug. 2012. F. Frustaci, M. Alioto, P. Corsonello, “Tapered-Vth Approach for Energy-Efficient CMOS Buffers,” IEEE Trans. on Circuits and Systems – part I, vol. 58, no. 11, pp. 2698-2707, Nov. 2011. M. Alioto, E. Consoli, G. Palumbo, “From Energy-Delay Metrics to Constraints on the Design of Digital Circuits,” in print on International Journal of Circuit Theory and Applications, available at http://onlinelibrary.wiley.com/doi/10.1002/cta.757/pdf M. Alioto, “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” IEEE Trans. on Circuits and Systems – part I (invited), vol. 59, no. 1, pp. 3-29, Jan. 2012. M. Alioto, ”Modeling Strategies of the Input Admittance of RC Interconnects for VLSI CAD Tools,” Microelectronics Journal (Elsevier), vol. 42, no. 1, pp. 63-73, Jan. 2011. M. Alioto, M. Poli, G. Palumbo, “Optimized Design of Parallel Carry-Select Adders,” Integration – the VLSI Journal (Elsevier), vol. 44, no. 1, pp. 62-74, Jan. 2011. M. Alioto, S. Badel, Y. Leblebici, “Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff,” Microelectronics Journal (Elsevier), vol. 41, no. 10, pp. 669-679, Oct. 2010. P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, ”Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements,” IEEE Trans. on VLSI Systems, vol. 19, no. 9, pp. 1569-1582, Sept. 2011. M. Alioto, ”Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells,” IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 751-762, May 2011. M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II – Results and Figures of Merit,” IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 737-750, May 2011. M. Alioto, E. Consoli, G. Palumbo, ”Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies,” IEEE Trans. on VLSI Systems, vo. 19, no. 5, pp. 725-736, May 2011. M. Alioto, “ Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1597-1607, July 2010. M. Alioto, E. Consoli, G. Palumbo, “General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1583-1596, July 2010. M. Alioto, E. Consoli, G. Palumbo, “Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 6, pp. 1273-1286, June 2010. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy,” in the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 879-895, 2010. M. Alioto, G. Palumbo, M. Poli, “Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates,” in print on International Journal of Circuit Theory and Applications M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic Circuits,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 2, pp. 355-367, Feb. 2010. M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 697-710, May 2010. M. Alioto, M. Poli, S. Rocchi, “A general power model of Differential Power Analysis attacks to static logic circuits,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 711-724, May 2010. A. Tajalli, M. Alioto, Y. Leblebici, “Improving power-delay performance of ultralow-power subthreshold SCL circuits,” IEEE Trans. on Circuits and Systems – part II, vol. 56, no. 2, pp. 127-131, Feb. 2009. M. Alioto, M. Poli, S. Rocchi, “Differential Power Analysis Attacks to Precharged Busses: a General Analysis for Symmetric-Key Cryptographic Algorithms,” IEEE Trans. on Dependable and Secure Computing, vol. 7, no. 3, pp. 226-239, July-Sept. 2010. M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology," IEEE Trans. on VLSI Systems, vol.18, no.2, pp. 232-245, Feb. 2010. M. Alioto, G. Palumbo, M. Poli, "Analysis and Modeling of Energy Consumption in RLC Tree Circuits," IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291, Feb. 2009. M. Alioto, G. Palumbo, "Power-Aware Design of Nanometer MCML Tapered Buffers," IEEE Trans. on Circuits and Systems – part II, vol. 55, no. 1, pp. 16-20, Jan. 2008. M. Alioto, G. Palumbo, "Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders," IEE Electronics letters, vol. 43, no. 13, pp. 707-709, 21st June 2007. M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Power-Delay-Area-Noise Margin Trade-offs in Positive-Feedback Source-Coupled Logic Gates," IEEE Trans. on Circuits and Systems – part I, vol. 54, no. 9, pp. 1916-1928, Sept. 2007. M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers," IEEE Trans. on Circuits and Systems – part II, vol. 54, no. 6, pp. 484-488, June 2007. T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli, "A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map", IEEE Trans. on Circuits and Systems - part I, vol. 54, no. 4, pp. 816-828, April 2007. M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder Topologies for High-Performance Low-Power Arithmetic Circuits," Microelectronics Journal, vol. 38, no. 1, pp. 130-139, Jan. 2007. M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison," IEEE Trans. on VLSI Systems, vol. 14, no. 12, pp. 1322-1335, Dec. 2006. M. Alioto, G. Palumbo, "Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59, 2006. M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1165-1169, Nov. 2006. M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting Hysteresys in MCML Circuits", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1170-1174, Nov. 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006. M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC Tree Circuits", IEEE Trans. on VLSI Systems, vol. 14, no. 5, pp. 452-461, May 2006. M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", IEE Electronics Letters, vol. 42, no. 4, pp. 211- 212, 16th February 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE Transactions on CAS – Part II, vol. 53, no. 5, pp. 329-333, May 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator," IEEE Transactions on CAS – Part I, vol. 53, no. 2, pp. 326-337, Feb. 2006. M. Alioto, G. Palumbo, "Modeling and Design Considerations on CML Gates under High-Current Effects," International Journal of Circuit Theory and Applications, vol. 33, no. 6, pp. 503-518, Nov./Dec. 2005. M. Alioto, G. Palumbo, "Design strategies of Cascaded CML Gates," IEEE Transactions on CAS – part II, vol. 53, no. 2, pp. 85-89, Feb. 2006. International conferences (2006-today)O. Aiello, P. Crovetti, M. Alioto, “A Sub‐Leakage pW‐Power Hz Range Relaxation Oscillator Operating with 0.3V‐1.8V Unregulated Supply,” accepted to VLSI Symposium 2018 L. Lin, S. Jain, M. Alioto, “A 595pW 14pJ/cycle Microcontroller with Dual-mode Standard Cells and Self-startup for Battery-Indifferent Distributed Sensing,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2018, pp. 44-45 Q. K. Trinh, S. Ruocco, M. Alioto, “Novel Time-Based Sensing Scheme for STT-MRAMs,” in print on Proc. of ISCAS 2018 O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V,” in print on Proc. of ISAS 2018 A. Alvarez, G. Ponnusamy, M. Alioto, “EQSCALE: Energy-Quality Scalable Feature Extraction Engine for Sub-mW Real-time Video Processing with 0.55 mm2 Area in 40nm CMOS,” in Proc. of ASSCC 2017, pp. 241-244 , Seoul (Korea), Nov. 2017 S. Taneja, A. Alvarez, G. Sadagopan, M. Alioto, “A Fully-Synthesizable C-Element Based PUF Featuring Temperature Variation Compensation with Native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm,” in Proc. of ASSCC 2017, pp. 301-304, Seoul (Korea), Nov. 2017 L. Lin, S. Jain, M. Alioto, “Reconfigurable Clock Networks for Random Skew Mitigation from Sub-Threshold to Nominal Voltage,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 440-441 M. Alioto, “Energy-Quality Scalable Adaptive VLSI Circuits and Systems beyond Approximate Computing,” in Proc. of IEEE DATE 2017 (invited), Lausanne (Switzerland), pp. 127-132, March 2017 R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, “A Variation-Aware Simulation Framework for Hybrid CMOS/Spintronic Circuits,” in Proc. of ISCAS 2017 M. Alioto, G. Scotti, A. Trifiletti, “Design-Oriented Models for Quick Estimation of Path Delay Variability via the Fan-Out-of-4 Metric,” in print on Proc. of ISCAS 2017 L. Lin, K. Trinh Quang, M. Alioto, “Transistor Sizing Strategy for Simultaneous Energy-Delay Optimization in CMOS Buffers,” in print on Proc. of ISCAS 2017 D. Esposito, A. G. M. Strollo, M. Alioto, “Power-Precision Scalable Latch Memories,” in print on Proc. of ISCAS 2017 S. Jain, M. Alioto, “A Closed-form Energy Model for VLSI Circuits under Wide Voltage Scaling,” in Proc. of ICECS 2016, pp. 548-551, Monaco, Dec. 2016 S. Timarchi, M. Alioto, “Ultra-Low Voltage Standard Cell Libraries: Design Strategies and a Case Study,” in Proc. of ICECS 2016, pp. 520-523, Monaco, Dec. 2016 V. Peluso, A. Calimera, E. Macii, M. Alioto, “Ultra-Fine Grain Vdd-Hopping for Energy-Efficient Multi-Processor SoCs,” in Proc. of VLSI-SoC 2016, pp. 1-6 , Tallinn (Estonia), Sept. 2016 Y. Zhang, M. Khayatzadeh, K. Yang, M.
Saligane, M. Alioto, D. Blaauw, D. Sylvester, “iRazor: 3-Transistor
Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor,” in
IEEE ISSCC Dig. Tech. Papers, Feb. 2016, pp. 160-161 M. Khayatzadeh, M. Saligane, J. Wang, M.
Alioto, D. Blaauw, D. Sylvester, “A Reconfigurable Dual Port Memory with Error
Detection and Correction in 28nm FDSOI,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2016, pp. 310-311 K. T. Quang, S. Ruocco, M. Alioto, “Boosted
Sensing for Enhanced Read Stability in STTMRAMs,” ISCAS 2016,
pp. Montreal (Canada), May 2016
K. T. Quang, S. Ruocco, M. Alioto, “STT-MRAM
Write Energy Minimization via Area Optimization Under Dynamic Voltage Scaling,” ISCAS 2016, Montreal (Canada), May 2016
M. Khayatzadeh, F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “A Reconfigurable Sense Amplifier with 3X Offset Reduction in 28nm FDSOI CMOS,” in Proc. of IEEE Symposium on VLSI Circuits, 2015, pp. 5–9 M. Alioto, E. Consoli, G. Palumbo, “Comparative
Analysis of the Robustness of Master-Slave Flip-Flops Against Variations,”
accepted to ICECS 2015, Cairo (Egypt), Dec. 2015 F. Frustaci, D. Blaauw, D. Sylvester, M.
Alioto, “Better-than-Voltage Scaling Energy Reduction in Approximate SRAMs via
Bit Dropping and Bit Reuse,” in Proc. of PATMOS 2015, Salvador (Brazil), Sept
2015 Massimo Alioto, Gaetano Palumbo, Elio Consoli, “PVT Variations in Differential Flip-Flops: A Comparative Analysis,” in Proc. of ECCTD 2015, Trondheim (Norway) Massimo Alioto, Gaetano Palumbo, Elio Consoli, “Variability Budget in Pulsed Flip-Flops,” in Proc. of NEWCAS 2015, Grenoble (France), June 2015 W. Zhao, Y. Ha, M. Alioto, “AES Architectures for Minimum-Energy Operation and Silicon Demonstration in 65nm with Lowest Energy per Encryption,” in Proc. of ISCAS 2015, pp. 2349-2352, Lisbon (Portugal), May 2015 M. Shoaran, A. Tajalli, M. Alioto, Y. Leblebici, “Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators,” in Proc. of ISCAS 2015, pp. 157-160, Lisbon (Portugal), May 2015 K. Trinh Quang, S. Ruocco, M. Alioto, “Modeling the Impact of Dynamic Voltage Scaling on 1T-1J STT-RAM Write Energy and Performance,” in Proc. of ISCAS 2015, pp. 2313-2316, Lisbon (Portugal), May 2015 A. Alvarez, W. Zhao, M. Alioto, “15-fJ/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra/Inter PUF Hamming Distance Separation in 65nm,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 258-259. M. Alioto, D. Esseni, “Comparative Evaluation of Tunnel-FET Ultra-Low Voltage SRAM Bitcell and Impact of Variations,” in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison of Variations in Double Edge Triggered Flip-Flops,” in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 M. Alioto, D. Esseni, “Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits,” in proc. of ACM SBCCI 2014, Aracaju (Brazil), Sept. 2014 L. Artola, G. Hubert, M. Alioto, “Comparative SET Evaluation of Layout cells in FinFET Technology,” in print on proc. of ESREF 2014 D. Esseni, M. Alioto, “Device-Circuit Co-Design and Comparison of Ultra-Low Voltage Tunnel-FET and CMOS Digital Circuits,” in proc. of NEWCAS 2014, pp. 321-324, Trois-Riviere (Canada), June 2014 M. Alioto, S. Bongiovanni, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks Against a Bit Slice Implementation of the Serpent Block Cipher,” in print on proc. of MIXDES 2014 F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 244-245. L. Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto, “A 346um2 Reference-Free Sensor Interface for Highly Constrained Microsystems in 28nm CMOS,” in print on proc. of ASSCC 2013, Singapore, Nov. 2013. Y.-P. Chen, Y. Lee, J.-Y. Sim, M. Alioto, D. Blaauw, D. Sylvester, “45pW ESD Clamp Circuit for Ultra-Low Power Applications,” in print on proc. of CICC 2013, San Jose (USA), Sept. 2013. M. Tache,
V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, “Sizing for Static Noise Margins
Revisited,” in Proc. of VARI 2013, Karlsruhe (Germany), Sept. 2013. V. Beiu, A. Beg, W. Ibrahim, F. Kharbash, M. Alioto, “Enabling Sizing for Enhancing the Static Noise Margins,” in print on Proc. of ISQED 2013, Santa Clara (California), March 2013. S. Bang, D. Blaauw, D. Sylvester, M. Alioto, “Reconfigurable Sleep Transistor for GIDL Reduction in Ultra-Low Standby Power Systems,” in Proc. of CICC 2012, San Jose, California, Sept. 2012. M. Alioto, E. Consoli, J. Rabaey, “EChO Power Management Unit with Reconfigurable Switched-Capacitor Converter in 65 nm CMOS,” in Proc. of CICC 2012, San Jose, California, Sept. 2012. J. Richmond, M. John, L. Alarcon, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. R. Sanders, J. M. Rabaey, “Active RFID: A Perpetual Wireless Communications Platform for Sensors,” in print on Proc. of ESSCIRC 2012, Bordeaux (France), Sept. 2012. M. Alioto, G. Palumbo, M. Pennisi, “A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic,” in Proc. of ISCAS 2012, pp. 1576-1579, Seoul (Korea), May 2012. F. Crupi, P. Magnone, M. Alioto, J. Franco, G. Groeseneken, “Early Assessment of Emerging Technologies for VLSI Logic Circuits from Experimental Measurements,” in Proc. of ICSICT 2012 ( invited).E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional Push-Pull Pulsed Latch with 726 fJ•ps Energy Delay Product in 65nm CMOS,” in Proc. of ISSCC 2012, San Francisco (USA), Feb. 2012. M. Alioto, “'Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells,” in Proc. of ECCTD 2011, pp. 557-561, Linkoping (Sweden), Aug. 2011. F. Frustaci, P. Corsonello, M. Alioto, “Optimization and Evaluation of Tapered-VTH Approach for Energy-Efficient CMOS Buffers,” in print on Proc. of ECCTD 2011, Aug. 2011. F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Experimental Analysis of Buried SiGe pMOSFETs from the Perspective of Aggressive Voltage Scaling,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. D. Baccarin, D. Esseni, M. Alioto, “A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. M. Alioto, E. Consoli, G. Palumbo, “DET FF Topologies: A Detailed Investigation in the Energy-Delay-Area Domain,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. F. Frustaci, P. Corsonello, M. Alioto, “Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. M. Djukanovic, L. Giancane, G. Scotti, A. Trifiletti, M. Alioto, “Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. M. Alioto, “Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. M. Alioto, E. Consoli, G. Palumbo, “Nanometer Flip-Flops Design in the E-D Space,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. J. Mitard, L. Witters, M. Garcia Bardon, P. Christie, J. Franco, A. Mercha, P. Magnone, M. Alioto, F. Crupi, L.-A. Ragnarsson, A. Hikavyy, B. Vincent, T. Chiarella, R. Loo, J. Tseng, S. Yamaguchi, S. Takeoka, W.-W. Wang, P. Absil, T. Hoffmann, “Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD,” accepted to IEEE IEDM 2010, San Francisco (USA), Dec. 2010. K. Agawa, M. Alioto, W. Zhou, T.-T. Liu, L. Alarcon, K. Hajkazemshirazi, M. John, J. Richmond, W. Li, J. Rabaey, “Design and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains,” in Proc. of SASIMI2010, Taipei (Taiwan), Oct. 2010. M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits,” in print on Proc. of PATMOS 2010, Grenoble (France), Sept. 2010. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A Scalable Low-Entropy Detector to Counteract the Parameter Variability effects in TRBGs,” in print on Proc. IMTC 2010, Austin (USA), May 2010. M. Merrett, Y. Wang, M. Alioto, M. Zwolinski, “Design Metrics for RTL Level Estimation of Delay Variability Due to Intradie (Random) Variations,” in Proc. of ISCAS 2010, pp. 2498-2501, Paris (France), May 2010. P. Magnone, F. Crupi, M. Alioto, B. Kaczer, “Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits,” in Proc. of ISCAS 2010, pp. 1699-1702, Paris (France), May 2010. M. Alioto, “Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology,” in Proc. of ISCAS 2010, pp. 3204-3207, Paris (France), May 2010. M. Alioto, P. Bennati, R. Giorgi, “Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed,” in Proc. of ISCAS 2010, pp. 37-40, Paris (France), May 2010. M. Alioto, “Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits,” in Proc. of ISCAS 2010, pp. 1468-1471, Paris (France), May 2010. M. Alioto, E. Consoli, G. Palumbo, “Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency,” in Proc. of ISCAS 2010, pp. 321-324, Paris (France), May 2010. M. Alioto, E. Consoli, G. Palumbo, “Optimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study,” in Proc. of ICECS 2009, pp. 275-278, Hammamet (Tunisia), Dec. 2009. M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the Impact of Random Process Variations in CMOS Tapered Buffers,” in Proc. of ICECS 2009, pp. 57-60, Hammamet (Tunisia), Dec. 2009. M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Theoretical Analysis and Impact of Variations,” in Proc. of ICECS 2009, pp. 85-88, Hammamet (Tunisia), Dec. 2009. M. Alioto, E. Consoli, G. Palumbo, “Dependence of Differential Flip-Flops Performance on Clock Slope and Relaxation of Clock Network Design,” in Proc. of ICM 2009, pp. 110-113, Marrakech (Morocco), Dec. 2009. M. Alioto, M. Poli, S. Rocchi, “Low-Overhead Countermeasures to protect Pre-charged Busses against Power Analysis Attacks,” in Proc. of ICM 2009, pp. 159-162, Marrakech (Morocco), Dec. 2009. M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results,” in Proc. of ICM 2009, pp. 46-49, Marrakech (Morocco), Dec. 2009. M. Alioto, “Analysis and Evaluation of Layout Density of FinFET Logic Gates,” in Proc. of ICM 2009, pp. 106-109, Marrakech (Morocco), Dec. 2009. M. Alioto, E. Consoli, G. Palumbo, “Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,” in Proc. of ECCTD 2009, pp. 61-64, Antalya (Turkey), Aug. 2009. M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, “Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits,” in Proc. of ECCTD 2009, pp. 779-782, Antalya (Turkey), Aug. 2009. M. Alioto, E. Consoli, G. Palumbo, “Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits,” in Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009. M. Alioto, Y. Leblebici, “Analysis and Design of Ultra-Low Power Subthreshold MCML Gates,” in Proc. of ISCAS 2009, pp. 2557-2560, Taipei (Taiwan), May 2009. M. Alioto, “Understanding Loading Effects of RC Uniform Interconnects,” in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan), May 2009. M. Alioto, S. Badel, Y. Leblebici, “Optimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff,” in Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009. M. Alioto, “CAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies,” in Proc. of ICM 2008, pp. 154-157, Sharjah (United Arab Emirates), Dec. 2008. M. Alioto, M. Poli, G. Palumbo, “Compact and Simple Output Transition Time Model in Nanometer CMOS Gates,” in Proc. of ICM 2008, pp. 235-238, Sharjah (United Arab Emirates), Dec. 2008. M. Alioto, M. Poli, S. Rocchi, “Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA,” in Proc. of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008. M. Alioto, Y. Leblebici, “Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits,” in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008. ( INVITED)Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici, “Design of High Performance Subthreshold Source-Coupled Logic Circuits,” in Proc. of PATMOS 2008, pp. 21-30, Lisbon (Portugal), Sep. 2008. Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi, “Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction,” in Proc. of PATMOS 2008, pp. 31-41, Lisbon (Portugal), Sep. 2008. M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic,” in Proc. of PATMOS 2008, pp. 136-145, Lisbon (Portugal), Sep. 2008. M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the impact of process variations on static logic circuits versus fan-in,” in Proc. of ICECS 2008, pp. 137-140, Malta, Aug. 2008. M. Alioto, G. Palumbo, M. Poli, “Energy Evaluation in RLC Tree Circuits with Exponential Input,” in Proc. of ICECS 2008, pp. 578-581, Malta, Aug. 2008. M. Alioto, L. Fondelli, S. Rocchi, "Analysis and Performance Evaluation of Area-Efficient True Random Bit Generators on FPGAs", in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008. A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J. Brauer, "Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage", in Proc. of ISCAS 2008, pp. 145-148, Seattle (USA), May 2008. M. Alioto, G. Palumbo, M. Poli, "Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs", in Proc. of ISCAS 2008, pp. 2865-2868, Seattle (USA), May 2008. M. Alioto, G. Palumbo, "Power-Delay Optimization in MCML Tapered Buffers", in Proc. of ISCAS 2008, pp. 141-144, Seattle (USA), May 2008. M. Alioto, M. Poli, S. Rocchi, "A General Model for Differential Power Analysis Attacks to Static Logic Circuits", in Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008. M. Alioto, G. Palumbo, M. Poli, "Efficient and Accurate Models of Output Transition Time in CMOS Logic", Proc. of ICECS 2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007. M. Alioto, "A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic", Proc. of ICECS 2007, pp. 431-434, Marrakech (Morocco), Dec. 2007. M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RLC Tree Circuits", Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain), Aug. 2007. M. Alioto, G. Palumbo, "Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders", Proc. of ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007. M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms", Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug. 2007. M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs", Proc. of ESSDERC 2007, pp. 191-194, Munich (Germany), Sept. 2007. M. Alioto, G. Palumbo, "Delay Variability Due to Supply Variations in Transmission-Gate Full Adders", Proc. of ISCAS 2007, pp. 3732-3735, New Orleans (USA), May 2007. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Maximum-Period PRBGs Derived From A Piecewise Linear One-Dimensional Map", Proc. of ISCAS 2007, pp. 693-696, New Orleans (USA), May 2007. M. Alioto, G. Palumbo, "High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology", Proc. of ISCAS 2007, pp. 2998-3001, New Orleans (USA), May 2007. M. Alioto, G. Palumbo, "Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects", Proc. of SCAS 2007, pp. 3255-3258, New Orleans (USA), May 2007. M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Mixed Techniques to Protect Precharged Busses against Differential Power Analisys Attacks", Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May 2007. T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, "Implementation-Efficient Maximum-Period Nonlinear Congruential Generators", Proc. of IMTC 2007, Warsaw (Poland), May. 2007. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Efficient Post-Processing Module for a Chaos-based Random Bit Generator", Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec. 2006. M. Alioto, G. Palumbo, "Modeling of Delay Variability due to Supply Variations in Pass-Transistor and Static Full Adders", Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006. M. Alioto, R. Mita, G. Palumbo, "A Design Methodology for High-Speed Low-Power MCML Frequency Dividers", Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Entropy Enhancement in a Chaos-Based True Random Bit Generators", Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006. M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis", Proc. of PATMOS 2006, pp. 624-633, Montpellier (France), Sept. 2006. M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm", Proc. of PATMOS 2006, pp. 593-602, Montpellier (France), Sept. 2006. M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Technique to Design High Entropy Chaos-Based True Random Bit Generators", Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May 2006. M. Alioto, G. Palumbo, M. Poli, "Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs", Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006. M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Analysis and Design of MCML Gates with Hysteresis", Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006. M. Alioto, G. Palumbo, "Nanometer MCML Gates: Models and Design Considerations", Proc. of ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006. M. Alioto, G. Palumbo, "Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders", Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006. T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Uniform-Distributed Noise Generator Based on a Chaotic Circuit", Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006. |