Short videos

Energy-centric circuit/system design and green ICs

Highlights and technical achievements
  • 2018: first pW-range wake-up oscillator for IoT sensor nodes able to operate from 0.3V to 1.8V, avoidings the traditional need of additional power-hungry voltage regulation
  • 2018: first battery-indifferent microcontroller able to operate at minimum-power mode (sub-nW), or minimum-energy mode (aligned with best-in-class low-energy processors)
  • 2018: demonstration of reconfigurable microarchitectures down to pipestage granularity, for energy optimization under wide voltage scaling (from 1.2V down to 0.3V)
  • 2017: first reconfigurable clock network for wide voltage scaling (0.3-1.2V). Skew reduction (up to 3.5X) reduces Vmin by 110mV and energy by 1.4X in 40nm. Area overhead is only 1.8% 
  • 2017: first sub-mW accelerator for feature extraction in computer vision for IoT down to 55uW (19-49X lower power than previous state of the art)
  • 2017: first fully-synthesizable Physically Unclonable Function for hardware security
  • 2017: first pencil-and-paper variability-aware design methodology for design margin evaluation
  • 2015: most stable and highest-statistical quality Physically Unclonable Function with lowest energy for hardware-level security (10-15X better than previous state of the art)
    • A. Alvarez, W. Zhao, M. Alioto, “15-fJ/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra/Inter PUF Hamming Distance Separation in 65nm,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 258-259
  • 2015: AES cryptographic core with lowest energy (7X better than previous state of the art)
    • W. Zhao, Y. Ha, M. Alioto, “Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study,” in print on IEEE Trans. on VLSI Systems – available at
  • 2015: SRAM senseamp with smallest offset at iso-area (2-3X better than previous state of the art)
    • M. Khayatzadeh, F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “A Reconfigurable Sense Amplifier with 3X Offset Reduction in 28nm FDSOI CMOS,” in Proc. of IEEE Symposium on VLSI Circuits, 2015, pp. 5–9
  • 2014: SRAM memory first with scalable energy-quality tradeoff for ultra-low energy operation
    • F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 244-245
  • 2013: power gating and ESD circuits with lowest leakage down to tens of pWs (10-100X better than previous state of the art)
    • S. Bang, D. Blaauw, D. Sylvester, M. Alioto, “Reconfigurable Sleep Transistor for GIDL Reduction in Ultra-Low Standby Power Systems,” in Proc. of CICC 2012, San Jose, California, Sept. 2012
    • Y.-P. Chen, Y. Lee, J.-Y. Sim, M. Alioto, D. Blaauw, D. Sylvester, “45pW ESD Clamp Circuit for Ultra-Low Power Applications,” in print on proc. of CICC 2013, San Jose (USA), Sept. 2013
  • 2013: smallest ADC Analog-to-Digital converter with widely scalable energy/resolution/voltage (100X lower area than previous state of the art)
    • L. Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto, “A 346um2 Reference-Free Sensor Interface for Highly Constrained Microsystems in 28nm CMOS,” in proc. of ASSCC 2013, Singapore, Nov. 2013
  • 2012: first reconfigurable DC-DC converter for reduction of active-sleep-active transition energy (3X lower than previous state of the art)
    • M. Alioto, E. Consoli, J. Rabaey, “EChO Power Management Unit with Reconfigurable Switched-Capacitor Converter in 65 nm CMOS,” in Proc. of CICC 2012, San Jose, California, Sept. 2012
  • 2012: first ultra-low power mm-sized active RFID for perpetual operation (3 uW)
    • J. Richmond, M. John, L. Alarcon, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. R. Sanders, J. M. Rabaey, “Active RFID: A Perpetual Wireless Communications Platform for Sensors,” in print on Proc. of ESSCIRC 2012, Bordeaux (France), Sept. 2012
  • 2012: fastest/most energy-efficient pulsed latch (2.3X better than state of the art)
    • E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional Push-Pull Pulsed Latch with 726 fJ•ps Energy Delay Product in 65nm CMOS,” in Proc. of ISSCC 2012, San Francisco (USA), Feb. 2012
Some applications of interest
- machine intelligence (e.g., deep learning) and methods to embed inference and learning on a single chip, using an amalgamation of algorithm, circuit and low power techniques
- energy-quality scalable integrated circuit and system design
- ubiquitous and nearly-perpetual vision on a chip
- hardware security down to physical
- ubiquitous human behavior and situational/context awareness via on-chip learning from vision and audio (e.g., crowd monitoring, congestion prediction, occupancy monitoring for thermal/acoustic/visual comfort assurance, ubiquitous surveillance, object detection)
- on-chip intelligence for locally-small globally-big data
- supersensors with architectural support for mutual calibration, and self-calibrating wireless sensors in massive training class for ultra-low testing cost
- biomedical monitors
- integrated systems for unconventional interaction with mobile devices
- extremely miniaturized integrated circuits for distributed surveillance

Our research agenda: a pictorial view