Research Programme in Assuring Hardware Security by Design in Systems on Chip

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Message from the lead principal investigator

Project Overview
Chip-level hardware security has recently taken the center stage in informative articles for the public and other media, after being relegated to the scientific literature. This is due to the convergence of concurrent trends, such as the exponential diffusion of electronic identification for the access to personalized services (e.g., banking, electronic-ID), the dramatic reduction in cost and time for physical attacks to chips (due to technological advances). Concurrently, an exponential increase in the number of connected devices is taking place at the end of the mobile era and the beginning of the Internet of Things. Also, the semiconductor supply chain has become very fragmented geographically and in terms of players (driven by cost, and the rise of the semiconductor industry in some Asian countries).

In perspective, chip-level hardware security is going to be even more crucial in developed economies and progressive countries that are massively adopting technologies to enable and simplify several types of secure transactions (e.g., financial, public services, medical records), including Singapore. Furthermore, even larger demand for hardware security is expected from the widespread diffusion of transactions managed by shared public ledgers, as in the case of blockchains (e.g., crypto currency, and prospectively many other services based on the analogous technologies). Bitcoin wallet hacking has been already demonstrated, and is a fundamental threat to the development of blockchain.

The grand-goal of the SOCure project is to assure hardware security by design in Systems on Chip (SoC), introducing the unprecedented capability of withstanding the presence of untrusted on-chip Intellectual Properties (IPs), as well as physical attacks including advanced ones (e.g., invasive). The first capability permits to maintain existing system design methodologies of SoCs, allowing seamless integration in both existing and new architectures with no disruption in well-established industry design practice. Isolation among on-chip IPs is pursued through secure on-chip communications based on ultra-lightweight hardware. The second capability enables protection against physical attacks, which are now well known to be a fundamental and now widespread threat, and have been the focus of research only recently. On the architectural side, the SOCure framework pursues HW security with minimal area/energy overhead to be scalable and adoptable in systems with a wide range of complexity, from secure SoCs down to simpler systems such as secure Microcontroller Units. On the physical side, a thorough set of innovative techniques with low overhead and seamless integration with design flows is introduced to protect physical integrity and confidentiality of on-chip data. For the first time, in SOCure the HW security challenges are investigated by explicitly coupling architectures and physical protection. Such holistic approach permits to raise the level of security, and at the same time reduce the typically substantial silicon area and power overhead due to the security requirements.

In addition to scientific advances, SOCure aims to make an economic impact in Singapore, creating value through the introduction of technological innovation and the creation of synergy between the main players in the semiconductor supply chain. Technological innovation and alignment during the project of local companies will be explicitly pursued with the active participation of foundries, system integrators, and security evaluators. Such coordinated technological advances in hardware security are expected to make a major impact both locally and globally. In Singapore, HW-secure systems are of strategic, societal and economic importance (e.g., Smart Nation, cash-less society). On a global scale, it creates a new opportunity to deliver technologies worldwide to secure the semiconductor supply chain and next-generation chips for a wide range of applications, from e-identification, to IoT, wearables, e-payment, financial services, utility metering, industry 4.0,and prospectively implantable biomedical devices, components for automotive, brand protection (e.g., food chain), and blockchains, among the others.

Research thrusts
  • THRUST 1: Physical Threats And Countermeasures
  • THRUST 2: Secure Architectures
  • THRUST 3: Security Analysis And Evaluation
  • THRUST 4: System Design, Integration And Demonstration

The team

The adopted collaboration model embeds an adversarial component, splitting the team into two competing factions, the “blue team” and the “red team”. The blue team focuses on hardware countermeasures, whereas the red team independently performs attacks to defeat such countermeasures. 

Based on the expertise of the team members below, the two teams are structured. Overall, the SOCure team joints the unique capabilities of research laboratories with world-class expertise and capabilities in terms of access to CMOS technologies, industry-standard design tools, testing equipment, collaboration with semiconductor industry, security evaluation and attacks.


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