Research Programme in Assuring Hardware Security by Design in Systems on Chip


The SOCure project is inter-disciplinary and lies at the intersection of physical countermeasure against hardware attacks, secure architectures and on-chip communications, energy-efficient Systems on Chip and lightweight primitives for hardware security. The PIs cover a strong hardware-centric and hardware security expertise, with each PI having proven leadership in each of the above fields. The unique capabilities and the international standing of the PIs is summarized below (see also “Curriculum Vitae of PIs and collaborators” section). Their contribution to each task is summarized below, and detailed in the “Outcomes & deliverables” section. The SOCure team also includes international collaborators to leverage their unique expertise and strengthen the team capabilities, as well as industrial partners that will provide support (see letters of interest) and application-driven perspective. Their support assures full relevance of the scientific investigation to the industrial interest, and alignment with the requirements of the existing hardware security ecosystem.

The adopted collaboration model embeds an adversarial component, splitting the team into two competing factions, the “blue team” and the “red team”. The blue team focuses on hardware countermeasures, whereas the red team independently performs attacks to defeat such countermeasures. 

Based on the expertise of the team members below, the two teams are structured. Overall, the SOCure team joints the unique capabilities of research laboratories with world-class expertise and capabilities in terms of access to CMOS technologies, industry-standard design tools, testing equipment, collaboration with semiconductor industry, security evaluation and attacks.

Lead Principal Investigator

Massimo Bruno Alioto


Massimo Alioto was born in Brescia in 1972. He took the M.Sc. degree in Electronic Engineering in 1997, and the Ph.D. degree in 2001 from the University of Catania. He is currently Associate Professor at the ECE department of the National University of Singapore, where he leads the Green IC group and is Director of the Integrated Circuits and Embedded Systems area.

In 2002, he joined the Department of Information Engineering of the University of Siena as a Research Associate, where he became Assistant Professor (2002) and Associate Professor (2005). In the summer of 2007, he was visiting professor at EPFL - Lausanne (Switzerland). In 2009-2011, he was visiting professor at the Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley. In 2011-2012, he was visiting professor at the University of Michigan, Ann Arbor. In 2013, he was visiting scientist at Circuit Research Lab - Intel Labs (Hillsboro, OR - USA).

His research interests involve extremely energy-efficient integrated circuits and systems, with his research activity being focused on:

· design of ultra low-power circuits and systems for distributed sensing and ubiquitous computing (e.g., IoT, wearables), including processing, memories, on-chip links, power management, analog interfaces, security, energy harvesting

· energy-quality scalable integrated systems for adaptive and dynamic management of the error-quality tradeoff

· always-on accelerators for data sensemaking and learning systems (vision, audio, gas sensors)

· energy efficiency and resiliency in near-threshold circuits for green computing (from circuits to microarchitectures)

· hardware-level security (crypto, physically unclonable functions, circuit-network protocol co-integration)

· circuit design in emerging technologies.

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Co - Principal Investigators


Shivam Bhasin

Senior Research Scientist

Shivam Bhasin (M’09) was born in India in 1985. He received the B.Tech. degree in electrical engineering from Uttar Pradesh Technological University, India in 2007, M.Sc degree in security of integrated circuits from Ecole Nationale Supérieure des Mines de St Etienne, France 
in 2008 and the Ph.D. degree for logic level countermeasures to secure FPGA-based design from Télécom ParisTech, France in 2011.

From 2012 to 2014, he was a postdoctoral research engineer with Institut Mines-Télécom, France where he was involved with projects on hardware security, design time security evaluations and hardware trojans. In 2015, he joined Temasek Labs@Nanyang Technological University (TL@NTU), Singapore as a Research Scientist and soon took over the leadership Physical analysis and cryptographic engineering (PACE) group as a principal investigator. Currently, he holds Senior research scientist position and Programme manager of cryptographic engineering at Centre of hardware Assurance at TL@NTU. Meanwhile, he has held an adjunct professorship at Indian Institute of Technology, Kharagpur, India since 2018, and is continuing his research in hardware security, implementation level attacks and secjure designs. 

Dr. Bhasin has published over 80 papers in top-tier journal and conferences, and holds one international patent. His work also forms part of several ISO standards in security evaluation.

Trevor Erik Carlson 

Assistant Professor

Trevor E. Carlson is an Assistant Professor of Computer Science at the School of Computing at the National University of Singapore (NUS). He earned B.S. and M.S. degrees in Electrical and Computer Engineering from Carnegie Mellon University in 2002 and 2003, and his Ph.D. in Computer Science Engineering from Ghent University in 2014. 

His research interests include highly-efficient microarchitectures, hardware/software co-design, performance modeling and fast and scalable simulation methodologies. Through the use of fast bottleneck analysis and simulation, his goal is to improve both performance and efficiency of next-generation processors. Dr. Carlson has over a decade of computer architecture experience covering both industry and academia. While a staff engineer at IBM from 2003 and 2007, he helped to author 4 issued patents. During his PhD, in collaboration with the Intel ExaScience Lab, he co-developed the Sniper Multi-core Simulator which is being used by hundreds of researchers to evaluate the performance and power-efficiency of next generation systems. As a researcher at imec, Belgium, and as a postdoctoral researcher at Uppsala University, Sweden, he investigated processor architectures to more efficiently handle long-latency memory accesses. Dr. Carlson’s research has been published at leading journals and conferences in computer architecture and simulation such as the International Symposium on Computer Architecture, the International Symposium on Microarchitecture, the International Symposium on High Performance Computer Architecture and the International Symposium on Performance Analysis of Systems and Software. 

Dr. Carlson has received a number of awards for his research into simulation, sampling and modeling. He is a recipient of the Best Paper Award at the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation in 2016, and the Best Paper Award at the International Symposium on Performance Analysis of Systems and Software in 2013. In addition, he has received two Best Paper Award nominations, one from the International Symposium on Performance Analysis of Systems and Software in 2015 and one from the International Symposium on Performance Analysis of Systems and Software in 2014. He was selected to attend the Heidelberg Laureate Forum as an outstanding young researcher with Turing, Fields and Abel Award winners in 2015, and his work with the Sniper Multi-Core Simulator received the HiPEAC Technology Transfer Award in 2013.

Anupam Chattopadhyay 

Assistant Professor

Anupam Chattopadhyay (Senior Member, IEEE) received the B.E. degree from Jadavpur University, India, in 2000, the M.Sc. degree from ALaRI, Switzerland, in 2002, and the Ph.D. degree from RWTH Aachen, Germany, in 2008.

From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen as a Junior Professor. Since September 2014, he has been an Assistant Professor at the School of Computer Science and Engineering (SCSE), Nanyang Technological University (NTU), Singapore and also holds an honorary adjunct appointment at SPMS, NTU. In the past, he was a Visiting Professor at EPFL, Switzerland and Indian Statistical Institute, Kolkata. His research advances has been reported in more than 100 conference/ journal papers (ACM/IEEE/Springer), multiple research monographs and edited books (CRC, Springer) and open-access forums. Together with his doctoral students, he proposed novel research directions like, domainspecific high-level synthesis for cryptography, high-level reliability estimation flows for embedded processors, generalization of classic linear algebra kernels, and multilayered coarse-grained reconfigurable architecture. His research in the area of emerging technologies has been covered by major news outlets across the world, including Asian Scientist, Straits Times, and The Economist.

Prof. Chattopadhyay received a Borcher’s plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008 and the nomination for best IP award at DATE 2016.


Gwee Bah Hwee 

Associate Professor

Dr Bah-Hwee Gwee received his B.Eng degree from University of Aberdeen, UK, in 1990.   He received his MEng and PhD degrees from Nanyang Technological University in 1992 and 1998 respectively.    He was an Assistant Professor of School of EEE, NTU from 1999 to 2005.   He is currently an Associate Professor cum Assistant Chair (Outreach) in School of EEE, NTU.   He has worked on a number of research projects with research grant amounting to S$15m (~US$10m).    He was the principal investigator of the research projects from MoE Academic Research Tier-2 grant of S$1.3m (~US$860k), ASEAN-EU University Network Programme grant of €200k and the Defense Science Organization grant of S$3.25m (~US$2.32m).   He was also the Co-Principal Investigator of NTU-Panasonic research collaboration amounting to S$1m (~US$800k) and DARPA project of ~US$350k, Linkoping University – NTU joint research collaboration of S$660k (~US$400k), The Agency for Science, Technology and Research (A*STAR) – PSF research project of S$700k ((USD500k).   His research interests include machine learning, hardware security, image processing, asynchronous circuit design, Class-D amplifiers, digital signal processing.   He has published more than 100 technical papers, 6 filed US patents and 3 granted US and started a Start-up Company in 2005. 

He was the Chairman of IEEE-Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016.   He is the Chairman of IEEE Circuits and Systems Society – DSPTC (2010-2020) and DSP Track Chair for ISCAS 2018-2020).   He was the General Co-Chair for IEEE DSP 2018 and IEEE SOCC 2019.   He was the organizing committee for IEEE Bio-CAS 2004, IEEE APCCAS 2006 and TPC Chairs for ISIC 2007, ISIC 2011 and ISIC 2016.   He has also served as Associate Editors for a number of journals, including IEEE Transactions of Circuits and Systems II – Brief Express in 2010-2011, 2018-2019 and 2020-2021, IEEE Transactions of Circuits and Systems I – Regular Papers in 2012-2013 and Journal of Circuits, Systems and Signal Processing in 2007-2012. He was awarded Temasek Laboratories @ NTU Best Publication Award in 2012 and the Teaching Excellence Award in 2013. He was awarded the Singapore Defence Technology Prize in 2016. He was an IEEE Distinguished Lecture for Circuits and Systems Society in 2009-2010 and in 2017-2018.

Abraham (Avi) Mendelson


Prof. Mendelson has extensive industrial experience, having worked as Principle Engineer at Intel corp. (Israel), National Semiconductors, consultant for Shannon Labs – Huawei, and as CTO of Optitura ltd. He is the architect of the chip multi-processor feature of Intel CoreDue family of processors with focus on core power management, which is the first multicore architecture that has been commercialized. He has also proven expertise in secure architectures, with emphasis on IP theft, reverse engineering, and Trojan/anomaly detection.


PEH Li Shiuan

Provost’s Chair Professor

Peh Li Shiuan joins NUS as Provost’s Chair Professor in the Department of Computer Science, with a courtesy appointment in the Department of Electrical and Computer Engineering in September 2016. Previously, she was Professor of Electrical Engineering and Computer Science at MIT and was on the faculty of MIT since 2009. She was also the Associate Director for Outreach of the Singapore-MIT Alliance of Research & Technology (SMART). Prior to MIT, she was on the faculty of Princeton University from 2002. She graduated with a Ph.D. in Computer Science from Stanford University in 2001, and a B.S. in Computer Science from the National University of Singapore in 1995. Her research focuses on networked computing, in many-core chips as well as mobile wireless systems. She received the IEEE Fellow in 2017, NRF Returning Singaporean Scientist Award in 2016, ACM Distinguished Scientist Award in 2011, MICRO Hall of Fame in 2011, CRA Anita Borg Early Career Award in 2007, Sloan Research Fellowship in 2006, and the NSF CAREER award in 2003.

Biplab Sikdar

Associate Professor

Biplab Sikdar received the B.Tech. degree in electronics and communication engineering from North Eastern Hill University, Shillong, India, in 1996, the M.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1998, and the Ph.D. degree in electrical engineering from the Rensselaer Polytechnic Institute, Troy, NY, USA, in 2001. He was on the faculty of Rensselaer Polytechnic Institute from 2001 to 2013, first as an Assistant and then as an Associate Professor. He is currently an Associate Professor with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore. His research interests include wireless network, and security for IoT and cyber physical systems. Dr. Sikdar is a member of Eta Kappa Nu and Tau Beta Pi. He served as an Associate Editor for the IEEE Transactions on Communications from 2007 to 2012. He currently serves as an Associate Editor for the IEEE Transactions on Mobile Computing.




Alexander Fish received the B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology, Haifa, Israel, in 1999. He completed his M.Sc. in 2002 and his Ph.D. (summa cum laude) in 2006, respectively, at Ben-Gurion University in Israel. He was a postdoctoral fellow in the ATIPS laboratory at the University of Calgary (Canada) from 2006-2008. In 2008 he joined the Ben-Gurion University in Israel, as a faculty member in the Electrical and Computer Engineering Department. There he founded the Low Power Circuits and Systems (LPC&S) laboratory, specializing in low power circuits and systems. In July 2011 he was appointed as a head of the VLSI Systems Center at BGU. In October 2012 Prof. Fish joined the Bar-Ilan University, Faculty of Engineering as an Associate Professor and the head of the Nanoelectronics track. In March 2015, he founded the Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Labs. Currently, he is a Full Professor and heads the EnICS Impact Center. 

Prof. Fish’s research interests include power reduction methodologies for high speed digital and mixed signal VLSI chips, energy efficient SRAM and eDRAM memory arrays, CMOS image sensors and biomedical circuits, systems and applications and hardware security . He has authored and co-authored over 170 scientific papers in journals and conferences, including IEEE Journal of Solid State Circuits, IEEE Transactions on Electron Devices, IEEE Transactions on Circuits and Systems and many others. He he has also submitted more than 30 patent applications of which 15 have been  granted. Prof. Fish has published three book chapters and one book as an editor. He was a co-author of papers that won the Best Paper Finalist awards at IEEE ISCAS and ICECS conferences.

Prof. Fish founded and served as an Editor in Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) from 2012-2018. He is an Associate Editor for the IEEE Sensors Journal, IEEE Access Journal, Microelectronics Journal (Elsiever) and Integration, the VLSI journal (Elsiever). He has also served as a chair of different tracks of various IEEE conferences. He was a co-organizer of many special sessions at IEEE conferences, including IEEE ISCAS, IEEE Sensors and IEEEI conferences. Prof. Fish is a member of Sensory, VLSI Systems and Applications and Bio-medical Systems Technical Committees of IEEE Circuits and Systems Society.




Dr. Osnat Keren’s interest in secure hardware began when she was studying codes for enhancing the reliability of hardware systems. She earned two degrees in Electrical Engineering from the Technion, pursued her PhD in coding theory at Tel Aviv University, and she worked as an algorithms developer in hi-tech companies. About twelve years ago she returned to academia, where she focused on spectral methods for logic design. Her research interests then turned to secure hardware.

Now a lecturer at BIU's Alexander Kofkin Faculty of Engineering, she remembers: “I became interested in this field due to an increasing need to mitigate malicious attacks on hardware system,” explains Dr. Keren. “Apparently, all existing methods of protecting these systems aimed to enhance their reliability and fail to provide security. I began searching for codes to detect attacks that may change the flow of the data and cause leakage of secrete or private information. In other words, I needed codes that can detect malicious attacks on hardware systems.”

A few years ago, Dr. Keren joined forces with Prof. Alex Fish, of the Faculty of Engineering’s Nano-Electronic study track, and the two begin developing circuit level countermeasures against non-invasive power analysis attacks. “Such attack enables the attacker to detect    a cryptographic secret key quite easily,” explains Dr. Keren.  This collaboration produced a unique approach to reduce the information leakage by reducing the correlation between the computed data and the profile of the consumed current. “This solution is unique in that it protects the system in the circuit level, and not in high abstraction levels such as the system’s architecture, algorithms, etc. It is this method’s main strength. If someone attempts to neutralize circuit level countermeasures, the chip will malfunction, and that will immediately annul the attack.”

Keren and Fish’s research group, which also includes a lab engineer and several graduate students, works in the (forming) Impact Research Center - EnICS Labs. The center, joined by several Engineering Faculty members, conducts studies on nanometric chips and leads dozens of collaborative projects with the local and international industry bodies and research groups.

Dr. Keren’s other research group, which also includes three graduate students, has recently listed in impressive accomplishment in detecting fault injection attacks. “Linear codes are widely used in the industry, thanks to the simplicity of their structure. As far as malicious attackers are concerned, these codes are ideal for side channel attacks since they can inject errors into the system, using lasers, voltage variations, etc., without being detected. Once injected, the system simply shifts from one legal state to another, in a way invisible to the user,” explains Dr. Keren. “One solution is to use nonlinear codes – unfortunately, those too, were vulnerable to certain error patterns and a strong attacker can tamper with the system without being noticed. So our objective was to find a way to build a nonlinear, robust code, which will detect any attack.



Ruby B. Lee is the Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science department. She is the director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Her current research is in designing security and new media support into core computer architecture, embedded systems and global networked systems, and in architectures resistant to Distributed Denial of Service attacks and Internet-scale epidemics. She teaches courses in Cyber Security and Processor Architectures for New Paradigms. She is a Fellow of the Association for Computing Machinery (ACM) and a Fellow of the Institute of Electrical and Electronic Engineers (IEEE). She is Associate Editor-in-Chief of IEEE Micro and Editorial Board member of IEEE Security and Privacy.

Prior to joining the Princeton faculty in 1998, Dr. Lee served as chief architect at Hewlett-Packard, responsible at different times for processor architecture, multimedia architecture and security architecture for e-commerce and extended enterprises. She was a key architect in the definition and evolution of the PA-RISC architecture used in HP servers and workstations, and also led the first CMOS PA-RISC single-chip microprocessor design. As chief architect for HP's multimedia architecture team, Dr. Lee led an inter-disciplinary team focused on architecture to facilitate pervasive multimedia information processing using general-purpose computers. This resulted in the first desktop computer family with integrated, software-based, high fidelity, real-time multimedia. Dr. Lee also co-led a multimedia architecture team for IA-64. Concurrent with full-time employment at HP, Dr. Lee also served as Consulting Professor of Electrical Engineering at Stanford University. She has a Ph.D. in Electrical Engineering and a M.S. in Computer Science, both from Stanford University, and an A.B. with distinction from Cornell University, where she was a College Scholar. She is an elected member of Phi Beta Kappa and Alpha Lambda Delta. She has been granted 115 United States and international patents, with several patents pending.



Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Professor Moore is the senior member of the Computer Architecture research group.



Dennis Sylvester is a Professor of Electrical Engineering and Computer Science, University of Michigan.

His research focuses on ultra-low power circuit design (analog, mixed-signal, and digital), small form-factor microsystems, and near-threshold computing. Applications of interest include implantable devices, environmental monitoring, as well as high-performance computing.