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IEEE JETCAS Special Issue on Energy-Quality Scalable Systems - Guest Editors: M. Alioto (NUS), V. De (Intel), A. Marongiu (ETHZ) - Paper submission now open

posted Sep 8, 2017, 10:41 PM by Massimo Alioto

The call for papers on "Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based" has just been released for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
Researchers are warmly invited to submit their paper contributions to be part of this highly impactful special issue in the area of energy-quality scalable sensing and computing, such as approximate sensing/computing, communication-inspired processing and learning-based systems that adapt the quality to the dataset, task, context and application, among the others.

Given its highly inter-disciplinary nature, contributions are welcome from authors working in the areas of circuits and systems, solid-state circuits, CAD, architectures, machine learning and signal processing (e.g., computer vision, audio). Please follow the instructions below, planning your submission to meet the deadline of Dec. 15, 2017.
For further information, you can contact Prof. Massimo Alioto.


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CALL for PAPERS
Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based



Guest Editors

Massimo Alioto*, National University of Singapore, malioto@ieee.org
Vivek De, Intel Labs, vivek.de@intel.com
Andrea Marongiu, ETH Zurich, a.marongiu@iis.ee.ethz.ch
* corresponding Guest Editor

Scope and Purpose

The historical 100X/decade energy down-scaling is currently being threatened by the slowing down of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions and tradeoffs that enable further energy reductions need to be explored.

As design dimension to continue the exponential energy down-scaling, ample opportunities have been recently demonstrated in energy-quality (EQ) scalable circuits and systems, which dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Energy-quality scalable designs minimize energy at run time, based on the actual quality target that is set by the specific task, the context (e.g., recent events, power/energy availability), and the specific dataset at hand (e.g., more/less complex or noisy data). EQ scalable systems indeed reduce energy by treating quality as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. However, such “just-enough” or “on-demand” quality management cannot be pursued based on traditional metrics that are only vaguely related to quality, or are application unspecific (e.g., error rate).

Thanks to their inherent resiliency against noise/errors/inaccuracies/approximations and hence strong potential for EQ scaling, prominent examples of relevant applications are multimedia, motion sensing/wearables, smart bio-sensors, smart sensors for the Internet of Things (IoT), machine learning (e.g., deep learning), computer vision, audio processing, speech recognition, physical data aquisition/processing, data analytics, among many others. Being application-dependent, the quality is quantified differently in each application domain through well-established metrics, such as accuracy/sensitivity/specificity in machine learning, PSNR (or other perceptive metrics) in video processing, false alarm rate in IoT sensors, misclassification rate in signal classification, SNR in signal processing, mean error distance in approximate digital circuits, perplexity in unsupervised learning, entropy in random key generation, effective resolution in analog-to-digital conversion, tracking length in visual object tracking, missed event detection rate in implantables and bio-medical circuits, among the others. 

From the state of the art viewpoint, various concepts and demonstrations that save energy at degraded quality have been proposed within the general framework of EQ-scalable circuits and systems, and have been mostly focused on processing. Some examples are approximate computing (e.g., precision adjustment, gate pruning), communication-inspired approaches (e.g., algorithmic noise tolerance, voltage/frequency overscaling), stochastic and probabilistic computing (e.g., robabilistic CMOS, emerging devices), learning-based approaches (e.g., adaptation via background or foreground on-chip training). Furthermore, we are witnessing an interesting convergence of EQ scalable systems and machine learning, where the noise resilience and the learning ability of machine learning circuits/algorithms can be leveraged to achieve graceful quality degradation (i.e., wider opportunities for energy saving), and allow significant circuit/architectural simplifications and imperfections by compensation with on-chip training. Also, various demonstrations on EQ-scalable System on Chip (SoC) building blocks with substantial energy reductions have also been presented, such as memories, analog-to-digital converters, microprocessors, accelerators for vision, and engines for machine learning.

At this juncture, several challenges need to be addressed to extract the energy gains expected from EQ scaling, while systematically and efficiently design truly scalable systems. For example, new methods and techniques to inexpensively insert EQ knobs in all SoC components are needed, from analog and sensor interfaces to processing, power management, algorithms, and software. As other challenges, quality needs to be inexpensively sensed at low area and energy/power penalty, to retain the potential energy advantages offered by EQ scaling. Methods and techniques are also needed to make the quality degradation graceful, to extend the energy savings when operating at lower quality. Novel design paradigms and optimization methodologies are also needed to supervise the energy-quality control, based on an underlying application-to-hardware framework. Novel frameworks are also needed to make EQ scaling techniques more generally applicable (e.g., general-purpose platforms), spanning multiple levels of abstraction (e.g., circuit, architecture, algorithm, software) and sub-systems. In addition, innovative frameworks and techniques are needed to minimize the overall energy via true adaptation (e.g., on-chip learning), while keeping quality within bounds in a real-time and context-aware fashion. 

The above challenges require a highly inter-disciplinary collective effort, as they lie at the intersection of circuits and systems, solid-state circuits, CAD, architectures, machine learning, signal processing (e.g., computer vision, audio), and the related communities. Accordingly, the authors of this special issue will be invited to submit their paper contributions on the following and other topics related to energy-quality scalable systems: 
  • sensors and circuits (analog, digital, power management) with the capability to dynamically trade off energy and quality
  • lightweight methods for quality enhancement and graceful degradation, from circuits (e.g., variation-resilient design, intentional under-design), to architectures (e.g., approximate), algorithms (e.g., quality-aware termination of iterative algorithms), and systems (e.g., context-aware systems for relaxed quality requirement)
  • run-time quality sensing, control and adaptation at different levels of abstraction (e.g., circuit, architecture) and in different sub-systems (e.g., analog, digital, power management)
  • relaxed sensor and circuit design via compensation of non-idealities through off/on-chip learning
  • architecture/algorithm/software overdesign elimination through “just-enough” quality assurance
  • dynamically scalable approximate, communication-inspired, stochastic, learning-based circuits and systems
  • HW/SW co-design approaches to adaptively manage the energy-quality tradeoff
  • design methodologies, programming models, language abstractions and compiler support for structured and disciplined energy-quality scaling in computation, communication and data transfer, including quality control and recovery from over-approximation
  • quality-aware middleware at all processing layers, from low-level runtime to high-level scheduling
  • quality modeling, monitoring and run-time adaptation in general-purpose and application-specific hardware
  • approximate, communication-inspired and learning-based frameworks that adapt the quality to the dataset, task, context and application
  • innovative case studies and emerging applications leveraging energy-quality scaling, with significant time- and energy-to-solution reduction (e.g., machine learning).

Important Dates
  • Manuscript submissions due: December 15th, 2017
  • First round of reviews completed: February 15th, 2018
  • Notification to authors: February 22nd, 2018
  • Revised manuscript submissions due: March 22nd, 2018
  • Second round of reviews completed: May 15th, 2018
  • Notification of acceptance: June 15th, 2018
  • Final manuscripts due: July 1st, 2018
  • Target publication date: September 2018

Submission Guidelines

All submitted manuscripts must (i) conform to JETCAS formatting requirements and page-count limits (from 8 to 14 pages – see guidelines at http://ieee-cas.org/pubs/jetcas/submit-manuscript); (ii) incorporate no less than 50% of new (previously unpublished) material; (iii) be submitted online at https://mc.manuscriptcentral.com/jetcas. Please note that you need to select “Special Issue on Energy-Quality Scalable Circuits and Systems for Sensing and Computing” when you submit a manuscript to this journal issue.

Copyright © IEEE Circuits and Systems Society, All rights reserved

New Springer book edited by Prof. Alioto: first book on chip design for IoT, from circuits to systems

posted Dec 7, 2016, 5:08 PM by Massimo Alioto   [ updated Dec 7, 2016, 5:10 PM ]

The book "Enabling the Internet of Things - from Integrated Circuits to Integrated Systems" is being published by Springer and is now available at

This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. (...)

For further details, visit the above Springer webpage.

http://www.springer.com/us/book/9783319514802

IEEE TCAS-I Special Issue on IoT (Guest Editors: M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli): paper submission now open

posted Aug 8, 2016, 1:23 AM by Massimo Alioto   [ updated Aug 8, 2016, 1:27 AM ]

The call for papers on "Circuits and Systems for the Internet of Things - From Sensing to Sensemaking" has just been released for the IEEE Trans. on Circuits and Systems - part I.
Researchers working in the space of the Internet of Things (IoT) are warmly invited to submit their paper contributions to be part of this highly impactful special issue.
The topic spans from sensing, to processing, to security and sensemaking (e.g., machine learning algorithms for on-chip knowledge extraction from sensed data). Emphasis is given to both "vertical" and "transversal" design methodologies and approaches that cross traditional design boundaries (see CfP below).

Please follow the instructions below, planning your submission to meet the deadline of Dec. 7, 2016.
For further information, you can contact Prof. Massimo Alioto.

TCAS I: Special Issue on CAS for the IoT - From Sensing to Sensemaking

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Call for Papers:
Special Issue on Circuits and Systems for the Internet of Things -
From Sensing to Sensemaking

The Internet of Things (IoT) is now at its onset as a result of a global effort to enable massively distributed integrated circuits and systems with sensing, processing, communication and energy management capabilities (the “IoTnodes”). The vision towards 1 Tera connected IoT nodes poses several challenges in the broad area of circuits and systems, including:
(i) the need for unprecedentedly high energy efficiency and low standby power,
(ii) ultra-low voltage operation and inexpensive resiliency-enhancement techniques,
(iii) very low cost across the entire chain from design to verification, and manufacturing,
(iv) systematic over-design margin elimination from the circuit to the application level,
(v) cyber-security assurance down to single chip level despite highly-constrained resources,
(vi) the need for early extraction of essential information from physical data within the IoT nodes themselves, to enable distributed learning/sensemaking and hence true IoT scalability.

Due to the gargantuan scale of the IoT, the above challenges need to be addressed through holistic approaches that embrace multiple levels of abstraction (verticality) and building blocks of the on-chip sensing/sensemaking chain (transversality). Nowadays, vertical approaches are progressively becoming more customary to exceed the artificial boundaries created by levels of abstraction, and enable advances that transcend their traditional limits. On the other hand, more research is needed to devise transversal methods that leverage the interaction within the sensing/sensemaking chain, from analog interfaces to processing, power delivery, wireless communications and HW/SW-level information security, while expanding into systems, data representation and algorithmic frameworks.

Authors are invited to submit Regular papers following the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) guidelines, within the remit of this Special Issue call. Topics within the remit of circuits and systems for IoTinclude (but are not limited to):

  • Circuit and system techniques for energy harvesting/delivery/management and tight coupling with analog/processing/communication sub-systems
  • Circuits and systems for ultra-low voltage, energy and standby power consumption
  • Adaptive and resilient analog and digital techniques for inexpensive counteraction of process/voltage/temperature variations
  • Highly power-efficient circuits for wireless communications in IoT
  • Energy-quality scalable and approximate circuits and systems for IoT
  • Heterogeneous, reconfigurable and other IoT-specific architectures
  • Circuit/architecture/system/algorithmic “just-enough” methods for over-design margin elimination at all levels of abstraction through adaptation to application, context, workload and dataset
  • Hardware-level security for IoT, from lightweight encryption to “physically unclonable functions” for chip authentication
  • System-on-chip design and verification methodologies for IoT
  • Circuit and system approaches and implications on data representation and algorithms for IoT
  • Circuits, systems and methods for on-chip machine learning and inference
  • Emerging technologies for IoT

Submission Guidelines
All submitted manuscripts must
(i) conform to TCAS-I’s formatting requirements and page-count limit (at no more than 14 pages);
(ii) incorporate no less than 50% of new (previously unpublished) material;
(iii) be submitted online at https://mc.manuscriptcentral.com/tcas1.

Please note that you need to select “Special Issue on IoT” when you submit a manuscript to this Special Issue.


Deadlines
Paper Submission:  December 7, 2016
Completion of First Review:  February 7, 2017
Completion of Final Review: April 7, 2017
Target Publication: June 2017


Guest Editors
Prof. Massimo Alioto
National University of Singapore (Singapore)
E-mail: malioto@ieee.org
 
Prof. Edgar Sanchez-Sinencio
Texas A&M University (USA)
e-mail: s-sanchez@tamu.edu
 
Prof. Alberto Sangiovanni-Vincentelli
University of California at Berkeley (USA)
E-mail: alberto@berkeley.edu

 

 

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Seminar on sub-10nm CMOS device-circuit interaction by Prof. Kaushik Roy (Purdue) - March 29, 2016

posted Mar 27, 2016, 6:30 PM by Massimo Alioto

DATE: 12-1:30PM on March 29, 2016        LOCATION: E1-06-09 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Device-Circuit Co-design of Multi-Gate FETs in Scaled Technologies


ABSTRACT

Sub-10nm FinFET scaling presents new challenges for technology and system designers. Leakage mechanisms such as direct source to drain tunneling (DSDT) through the channel barrier, which was uncommon in longer channel bulk MOSFETs, will start dominating for sub-10nm gate lengths, necessitating careful device design using quantum mechanical simulations. We analyze the impact of DSDT in underlapped/asymmetrically doped FinFETs using 2D ballistic Physics based simulations. The increase in the effective channel length resulting from using underlap leads to significant reduction in DSDT especially in nFinFETs where the majority carriers have a lower tunneling effective mass. By including the important leakage components such as DSDT, sub-threshold leakage and direct gate oxide tunneling in the device characteristics, we derive a compact model suitable for cell library characterization and synthesize a LEON3 microprocessor and a memory subsystem. Our system level simulation results suggest that overall power consumption in sub-10nm technologies will be dominated by DSDT. We also estimate the improvements possible by using fin thickness control as a means to overcome the on-current degradation arising from gate-underlap. Finally I will discuss device and circuit design issues related to steep slope tunnel FETs.





SHORT BIO
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Seminar on many-core energy-efficient architectures by Prof. Bevan Baas (UCDavis) - March 24, 2016

posted Mar 27, 2016, 6:17 PM by Massimo Alioto   [ updated Mar 27, 2016, 6:22 PM ]

DATE: 12-1:30PM on March 24, 2016        LOCATION: E1-06-05 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: A case for fine-grain processor arrays for efficient and high-performance computation


ABSTRACT

The continually-growing number of devices available per chip assures the presence of many processing blocks per die communicating by some type of inter-processor interconnect. It is interesting to consider what the granularity of the processing blocks should be given a fixed amount of die area. Between the domains of FPGAs and traditional processors lies a lightly-explored regime which we call fine-grain many-core, whose processors: can be programmed by simple C programs; typically operate with high throughput and high energy-efficiency; are well suited for deep submicron fabrication technologies; and are well matched to many DSP, multimedia, and embedded workloads, and—somewhat counterintuitively—also to some enterprise and scientific kernels.

The AsAP architecture is a fine-grain many-core system composed of a large number of programmable reduced-complexity processing elements with virtually no algorithm-specific hardware and with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS). Oscillators fully halt when there is no work to do, and restart at full speed in less than one cycle after work becomes available. Processors communicate through a reconfigurable full-rate circuit-switched mesh network and the third generation design includes a complementary very-small-area packet router.

An overview will be given of a fully-functional 36-processor chip and a 167-processor 1.2 GHz 65 nm chip with per-core dynamic supply voltage and dynamic clock frequency capabilities. Due to the MIMD architecture and individual near-optimal oscillator halting, the system operates with an energy per operation of 9.2 W at 1 trillion instructions/sec virtually independent of the system load. Several dozen kernels and applications have been coded with power, throughput, and area results comparing very well with solutions on available programmable processors. A simple C compiler and automatic mapping tool greatly simplify programming. A sneak preview of a third generation deep-submicron chip now being tested concludes the talk.


SHORT BIO

Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now a Professor.

Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, the Best Paper Award at the IEEE Intl Conference on Computer Design in 2011, Best Student Paper Award 3rd place at IEEE Intl MSCS 2015 and IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at DAC 2010, several Best Paper nominations, and he supervised the research that earned the College of Engineering Best Doctoral Dissertation Award Honorable Mention in 2013. From 2007-2012 he was an Associate Editor for the IEEE Journal of Solid-State Circuits. He has Co-Chaired and served on numerous conference program committees and has served as Guest Editor of several special issues.

Seminar on Carbon Nanotubes by Prof. Subhasish Mitra (Stanford) - June 26, 2015

posted Jun 18, 2015, 6:28 PM by Massimo Alioto

DATE: 12-1:30PM June 26, 2015        LOCATION: E5-03-23 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map)
TITLEFrom Nanodevices to Nanosystems: Carbon Nanotube N3XT Information Technology


ABSTRACT

Carbon Nanotube Field-Effect Transistors (CNFETs) can revolutionize the design of highly energy-efficient future electronic systems. Unfortunately, carbon nanotubes (CNTs) face major obstacles such as substantial imperfections and variations inherent to CNTs, and low CNFET current densities. 
A combination of CNFET circuit design and CNT processing techniques (the "imperfection-immune paradigm") overcomes these challenges to enable the experimental demonstration of the carbon nanotube computer, and, more generally, arbitrary CNFET digital systems. These are the first system-level demonstrations among promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems. 
We will also discuss new nanosystem architectures enabled by monolithic three-dimensional (3D) integration of CNFETs and emerging memories. Such fine-grained 3D integration allows for computation immersed in memory, and is key to achieving very high degrees of energy efficiency for emerging abundant-data applications. 
This research was performed at Stanford University in collaboration with Prof. H.-S. Philip Wong and several graduate students.



SHORT BIO
Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.

Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotube imperfection-immune digital VLSI, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, and the Intel Achievement Award, Intel’s highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.

Seminar on Approximate Computing by Prof. Kaushik Roy (Purdue) - June 23, 2015

posted Jun 18, 2015, 6:19 PM by Massimo Alioto   [ updated Jun 18, 2015, 6:20 PM ]

DATE: 2-3:30PM June 23, 2015        LOCATION: E5-03-23 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Approximate Computing for Energy-efficient Error-resilient Multimedia Systems

ABSTRACT
In today’s world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, mining and synthesis. These facts pose an interesting design challenge to process digital data in an energy-efficient manner while catering to desired user quality requirements. Most of these multimedia applications possess an inherent quality of "error"-resilience. This means that there is considerable room for allowing approximations in intermediate computations, as long as the final output meets the user quality requirements. This relaxation in "accuracy" can be used to simplify the complexity of computations at different levels of design abstraction, which directly helps in reducing the power consumption. At the algorithm and architecture levels, the computations can be divided into significant and non-significant. Significant computations have a greater impact on the overall output quality, compared to non-significant ones. Thus the underlying architecture can be modified to promote faster computation of significant components, thereby enabling voltage-scaling (at the same operating frequency). At the logic and circuit levels, one can relax Boolean equivalence to reduce the number of transistors and decrease the overall switched capacitance. This can be done in a controlled manner to introduce limited approximations in common mathematical operations like addition and multiplication. All these techniques can be classified under the general topic of “Approximate Computing”, which is the main focus of this talk.

SHORT BIO
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). 

Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Seminar on 3D systems by Prof. Yusuf Leblebici (EPFL) - Dec. 11, 2014

posted Dec 6, 2014, 9:18 AM by Massimo Alioto

DATE: 1-2PM Dec. 11, 2014        LOCATION: E5-03-20 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Design and Testing Strategies for Modular 3D-Multiprocessor / Memory Systems Integration Using Die-level TSV Technology

ABSTRACT
This talk offers a broad overview on 3D integration technologies, and also provides some outline / insight concerning architectural design implications. An innovative modular 3D stacked multi-processor architecture is presented.
The platform is composed of completely identical stacked dies connected together by Through-Silicon-Vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3D Network-on-Chip (NoC), which can route packets in the vertical direction. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90nm CMOS process and stacked using an in-house, Via-Last Cu-TSV process.
Test results show that the proposed 3D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gbps. The talk will also discuss high speed serial data transmission possibilities over TSVs and offer a systematic cost/benefit analysis of data serialization for processor/memory stacks.

SHORT BIO
Yusuf Leblebici (M'90-SM'98-F'09) received the B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, Istanbul, Turkey, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign (UIUC) , in 1990. Since 2002, he is a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of six textbooks, as well as more than 300 articles published in various journals and conferences. He is a Fellow of IEEE since 2010, and he has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.



New Springer book

posted Nov 13, 2014, 2:41 AM by Massimo Alioto

The book "Flip-Flop Design in Nanometer CMOS" has been published by Springer and is now available at


video of talk at HotChips 2014 on Internet of Things - state of the art and directions

posted Sep 3, 2014, 4:42 AM by Massimo Alioto

Prof. Alioto's talk at HotChips 2014 summarizes the current state of the art and provides technology directions for ultra-low power VLSI design for the Internet of Things.

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