Talk by Prof. Alberto Sangiovanni Vincentelli Department of EECS, University of California,Berkeley - 05 July 2018 Prof. Alberto Sangiovanni-Vincentelli (University of California, Berkeley) will give a talk on "REFLECTIONS ON INNOVATIONECOSYSTEMS: MY JOURNEY FROM THEORY RESEARCH TO
USD26BILLION". The talk will take place on July 05, 2018 at 12-2PM in THE HANGAR BY NUSENTERPRISE; 21 Heng Mui Keng Terrace Level 1,
Singapore 119613. All interested researchers, students and designers from industry are more than welcome to join. The details on the logistics and the talks are provided in the following. TOPIC: SPEAKER: Prof. Alberto Sangiovanni-Vincentelli - University of California, Berkeley, USA DATE: 05 July 2018, Thursday TIME: 12pm to 2pm VENUE: HE HANGAR BY NUSENTERPRISE; 21 Heng Mui Keng Terrace Level 1, Singapore 119613 |
News
New Springer book: world's first on reconfigurable microarchitectures for wide energy scaling
The book "Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling" is being published by Springer and is now available athttps://www.springer.com/gp/book/9783030387952This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.For further details, visit the above Springer webpage.The resources made available by our group to create your own design flow to develop reconfigurable microarchitectures in a fully automated manner are available here. |
MEAD course on "Energy-constrained integrated systems" organized by Prof. Alioto and Prof. Alarcon (UPC) - Asia's first!
The new course will be held from Dec. 10 to Dec 14, 2018 in Singapore at NUS. The flyer and the detailed schedule are attached below. Detailed information and the registration form are available at: http://mead.ch/MEADNEW/energy-constrained-integrated-systems/ SPEAKERS The course follows the long MEAD tradition of hosting world leaders as speakers:
RATIONALE AND SCOPE This MEAD course focuses on the design of systems-on-chip for those applications that impose a tight energy budget, as common requirement to achieve long lifetime, miniaturization and enhanced functionality in a small form factor, among the others. A tightly constrained energy budget is a common trait in several prominent applications, such as sensor nodes for the Internet of Things, wearables, biomedical and implantable devices, which the course covers through common design principles and techniques exploiting the application specificity. This course is structured as self-contained source of knowledge and insight for both circuit designers and system architects from industry, research institutions and academia. The course distinctively emphasizes the interaction between the circuit and the system level of abstraction, providing an understanding into how solid-state circuits need to be designed with the system in mind, and how systems need to be architected based on circuit capabilities and limitations. Design driven by the circuit-system interaction indeed allows to relax the fundamental design tradeoffs at both circuit and system level (e.g., leveraging algorithmic noise resiliency to tolerate circuit imperfections, exploiting ultra-low power always-on sensor interfaces to enable event-driven execution, or making wireless communication sporadic through more intelligent systems via ultra-low power processing techniques). Such "vertical" perspective enables synergy across levels of abstraction, and offers several opportunities to reduce the energy consumption, compared to separate circuit or system optimization. As further dimension that is distinctive of the course, circuit/system run-time co-adaptation is a common thread to reduce the circuit design margin and down-scale the system energy consumption, when the application, the task, the activation pattern, or the dataset allow. Adaptation indeed enables the exploitation of the application and the signal specificity, driving down the consumption (e.g., leveraging sparse representations to enable signal dimensionality reduction for reduced memory and wireless datarate, or exploiting circuits with run-time scalable energy-quality degradation to meet the time-varying accuracy requirement at minimum energy). The lectures are organized in a case-study fashion for immediate fruition, enabling the usage of design techniques and abstractions in practical cases, and bridging the gap between design principles and applications. The course covers the analysis of on-going and emerging technology trends in energy-constrained integrated systems, the fundamental design tradeoffs, and the design methodologies to manage such tradeoffs. Context-aware techniques for power management, wireless communications, sensor interfaces and processing are presented, where the signal and event pattern specificity are leveraged to reduce the energy at both circuit and system level. Energy-efficient on-chip sensor data sensemaking is also addressed from the perspective of signal processing and machine learning engines for detection/classification. Finally, several case studies are comparatively analyzed to link general design principles to silicon demonstrations, highlighting the “big ideas” that are (and will be) driving further advances in energy-constrained systems. |
Talk by Prof. Makoto Nagata (Kobe University - Japan) - 21 September 2018
Prof. Makoto Nagata (Kobe University - Japan) will give an exciting talk on "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security". The talk will take place on September 21, 2018 as follows: TOPIC: Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security SPEAKER: Prof. Makoto Nagata, Kobe University DATE: 21 September 2018, Friday TIME: 4pm to 5pm VENUE: E1-06-03, Engineering Block E1, Faculty of Engineering, NUS All interested researchers, students and designers from industry are more than welcome to join. The details on the logistics and the talks are also provided in the attached flyer. |
Seminar by Prof. Alberto Sangiovanni-Vincentelli (UCBerkeley) - May 17, 2018
Prof. Alberto Sangiovanni-Vincentelli (University of California, Berkeley) will give a talk on "LET'S GET PHYSICAL: ADDING PHYSICAL DIMENSIONS TO CYBER SYSTEMS". The talk will take place on May 17, 2018 at 12-1PM in E5-03-20. All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS. The details on the logistics and the talks are provided in the following. TOPIC: LET'S GET PHYSICAL: ADDING PHYSICAL DIMENSIONS TO CYBER SYSTEMS SPEAKER: Prof. Alberto Sangiovanni-Vincentelli - University of California, Berkeley, USA DATE: 17 May 2018, Thursday TIME: 12pm to 1pm VENUE: E5-03-20, Engineering Block E3, Faculty of Engineering, NUS In this presentation, I highlight the economic potential of CPS, their role in autonomous driving, and some of the design challenges due to the complexity, heterogeneity and power consumption of CPS. |
Seminar by Prof. Jan Rabaey (UCBerkeley) - May 15, 2018
Prof. Jan Rabaey (University of California, Berkeley) will give a talk on "Brain-like Cognitive Engineering Systems". The talk will take place on May 15, 2018 at 12-1PM in E3-06-01. All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS. The details on the logistics and the talks are provided in the following. TOPIC: Brain-like Cognitive Engineering Systems SPEAKER: Prof. Jan Rabaey - University of California, Berkeley, USA DATE: 15 May 2018, Tuesday TIME: 12pm to 1pm VENUE: E3-06-01, Engineering Block E3, Faculty of Engineering, NUS |
Seminar by Prof. Dennis Sylvester (Univ. Michigan) and Dr. Edith Beigné (CEA LETI) - April 4, 2018
Prof. Dennis Sylvester (Univ. Michigan) and Dr. Edith Beigné will be the protagonists of the seminar session on "The future of pervasive sensing and computing - A vision from technology leaders". The session will take place on April 4, 2018 at 12-2PM in EA-06-05. All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS. The details on the logistics and the talks are provided in the following. ![]() TOPIC: Circuits and Systems for Ultra-Low Power mm-Scale Microsystems SPEAKER: Prof Dennis Sylvester - University of Michigan, Ann Arbor, USA DATE: 4 April 2018, Wednesday TIME: 12pm to 1pm VENUE: EA-06-05, Engineering Block EA, Faculty of Engineering, NUS ABSTRACT: This talk will describe recent progress at the University of Michigan in circuit building blocks for complete wireless sensing systems on the millimeter-scale. It will also highlight a few example systems, particularly focusing on applications in the audio space. Major circuit blocks that will be described include power management, low-power embedded non-volatile memories, hardware security primitives, and sensors and relevant interface circuits. BIOGRAPHY: Dennis Sylvester is Professor of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. He received a PhD from the University of California, Berkeley and now is the Director of the Michigan Integrated Circuits Laboratory (MICL), a group of ten faculty and 70+ graduate students. He has held research staff positions in the Advanced Technology Group of Synopsys, Hewlett-Packard Laboratories, and visiting professorships at the National University of Singapore and Nanyang Technological University. He has published over 475 articles in his areas of interest, which include the design of millimeter-scale computing systems and energy efficient near-threshold computing. He holds 40 US patents and serves as a consultant and technical advisory board member for electronic design automation and semiconductor firms in these areas. He co-founded Ambiq Micro, a fabless semiconductor company developing ultra-low power mixed-signal solutions for compact wireless devices. He is an IEEE Fellow. TOPIC: The future of low power circuits and embedded intelligence: emerging devices and new design paradigms SPEAKER: Edith Beigné - Research Director of Integrated Circuits and System Division at CEA LETI DATE: 4 April 2018, Wednesday TIME: 1pm to 2pm VENUE: EA-06-05, Engineering Block EA, Faculty of Engineering, NUS ABSTRACT: Circuit and design division at CEA LETI is focusing on innovative architectures and circuits dedicated to digital, imagers, wireless, sensors, power management and embedded software. After a brief overview of adaptive circuits for low power multi-processors and IoT architectures, the talk will detail new technologies opportunities for more flexibility. Digital and mixed-signal architectures using 3D technologies will be presented in the scope of multi-processors activity as well as imagers and neuro-inspired circuits. Also, the integration of non-volatile memories will be shown in the perspective of new architectures for computing. Finally, embedding learning will be addressed to solve power challenges at the edge and in end-devices: some new design approaches will be discussed. BIOGRAPHY: Edith Beigné joined CEA-LETI, Grenoble, France, in 1998. She is the Research Director of Integrated Circuits and System Division at CEA LETI. Since 2009, she has been a senior scientist in the digital and mixed-signal design lab where she researches low power and adaptive circuit techniques, exploiting asynchronous design and advanced technology nodes like FDSOI 28nm and 14nm for many different applications from high performance MPSoC to ultra-low power IoT applications. Her main research interests today are low power digital circuits, neuro-inspired architectures and 3D integration. She is part of ISSCC TPC since 2014 and part of VLSI’ symposium since 2015. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. |
IEEE JETCAS Special Issue on Energy-Quality Scalable Systems - Guest Editors: M. Alioto (NUS), V. De (Intel), A. Marongiu (ETHZ) - Paper submission now open
The call for papers on "Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based" has just been released for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Researchers are warmly invited to submit their paper contributions to be part of this highly impactful special issue in the area of energy-quality scalable sensing and computing, such as approximate sensing/computing, communication-inspired processing and learning-based systems that adapt the quality to the dataset, task, context and application, among the others. Given its highly inter-disciplinary nature, contributions are welcome from authors working in the areas of circuits and systems, solid-state circuits, CAD, architectures, machine learning and signal processing (e.g., computer vision, audio). Please follow the instructions below, planning your submission to meet the deadline of Dec. 15, 2017.
|
New Springer book edited by Prof. Alioto: first book on chip design for IoT, from circuits to systems
The book "Enabling the Internet of Things - from Integrated Circuits to Integrated Systems" is being published by Springer and is now available at This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. (...) For further details, visit the above Springer webpage. |
IEEE TCAS-I Special Issue on IoT (Guest Editors: M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli): paper submission now open
The call for papers on "Circuits and Systems for the Internet of Things - From Sensing to Sensemaking" has just been released for the IEEE Trans. on Circuits and Systems - part I. Researchers working in the space of the Internet of Things (IoT) are warmly invited to submit their paper contributions to be part of this highly impactful special issue. The topic spans from sensing, to processing, to security and sensemaking (e.g., machine learning algorithms for on-chip knowledge extraction from sensed data). Emphasis is given to both "vertical" and "transversal" design methodologies and approaches that cross traditional design boundaries (see CfP below). Please follow the instructions below, planning your submission to meet the deadline of Dec. 7, 2016.
|
Seminar on sub-10nm CMOS device-circuit interaction by Prof. Kaushik Roy (Purdue) - March 29, 2016
DATE: 12-1:30PM on March 29, 2016 LOCATION: E1-06-09 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: Device-Circuit Co-design of Multi-Gate FETs in Scaled Technologies ![]() ABSTRACT Sub-10nm FinFET scaling presents new challenges for technology and system designers. Leakage mechanisms such as direct source to drain tunneling (DSDT) through the channel barrier, which was uncommon in longer channel bulk MOSFETs, will start dominating for sub-10nm gate lengths, necessitating careful device design using quantum mechanical simulations. We analyze the impact of DSDT in underlapped/asymmetrically doped FinFETs using 2D ballistic Physics based simulations. The increase in the effective channel length resulting from using underlap leads to significant reduction in DSDT especially in nFinFETs where the majority carriers have a lower tunneling effective mass. By including the important leakage components such as DSDT, sub-threshold leakage and direct gate oxide tunneling in the device characteristics, we derive a compact model suitable for cell library characterization and synthesize a LEON3 microprocessor and a memory subsystem. Our system level simulation results suggest that overall power consumption in sub-10nm technologies will be dominated by DSDT. We also estimate the improvements possible by using fin thickness control as a means to overcome the on-current degradation arising from gate-underlap. Finally I will discuss device and circuit design issues related to steep slope tunnel FETs. SHORT BIO Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE. |