Talk by Prof. Alberto Sangiovanni Vincentelli Department of EECS, University of California,Berkeley - 05 July 2018

Prof. Alberto Sangiovanni-Vincentelli (University of California, Berkeley) will give a talk on "REFLECTIONS ON INNOVATIONECOSYSTEMS: MY JOURNEY FROM THEORY RESEARCH TO USD26BILLION". The talk will take place on July 05, 2018 at 12-2PM in THE HANGAR BY NUSENTERPRISE; 21 Heng Mui Keng Terrace Level 1, Singapore 119613.
All interested researchers, students and designers from industry are more than welcome to join.
The details on the logistics and the talks are provided in the following.

SPEAKER: Prof. Alberto Sangiovanni-Vincentelli - University of California, Berkeley, USA
DATE: 05 July 2018, Thursday
TIME: 12pm to 2pm
VENUE: HE HANGAR BY NUSENTERPRISE; 21 Heng Mui Keng Terrace Level 1, Singapore 119613

ABSTRACT: In this talk, Prof. Alberto Sangiovanni-Vincentelli will describe his experiences in the different industrial ecosystems and which role University and industrial research, start-ups, established companies, and venture capital play in them. He will conclude with some considerations on how to make the Singapore entrepreneurial and University fabric even more effective than it is today.

MEAD course on "Energy-constrained integrated systems" organized by Prof. Alioto and Prof. Alarcon (UPC) - Asia's first!

posted Sep 26, 2018, 4:48 AM by Massimo Alioto   [ updated Sep 26, 2018, 4:56 AM ]

The new course will be held from Dec. 10 to Dec 14, 2018 in Singapore at NUS.
The flyer and the detailed schedule are attached below. Detailed information and the registration form are available at:

The course follows the long MEAD tradition of hosting world leaders as speakers:

This MEAD course focuses on the design of systems-on-chip for those applications that impose a tight energy budget, as common requirement to achieve long lifetime, miniaturization and enhanced functionality in a small form factor, among the others. A tightly constrained energy budget is a common trait in several prominent applications, such as sensor nodes for the Internet of Things, wearables, biomedical and implantable devices, which the course covers through common design principles and techniques exploiting the application specificity.
This course is structured as self-contained source of knowledge and insight for both circuit designers and system architects from industry, research institutions and academia. The course distinctively emphasizes the interaction between the circuit and the system level of abstraction, providing an understanding into how solid-state circuits need to be designed with the system in mind, and how systems need to be architected based on circuit capabilities and limitations. Design driven by the circuit-system interaction indeed allows to relax the fundamental design tradeoffs at both circuit and system level (e.g., leveraging algorithmic noise resiliency to tolerate circuit imperfections, exploiting ultra-low power always-on sensor interfaces to enable event-driven execution, or making wireless communication sporadic through more intelligent systems via ultra-low power processing techniques). Such "vertical" perspective enables synergy across levels of abstraction, and offers several opportunities to reduce the energy consumption, compared to separate circuit or system optimization.
As further dimension that is distinctive of the course, circuit/system run-time co-adaptation is a common thread to reduce the circuit design margin and down-scale the system energy consumption, when the application, the task, the activation pattern, or the dataset allow. Adaptation indeed enables the exploitation of the application and the signal specificity, driving down the consumption (e.g., leveraging sparse representations to enable signal dimensionality reduction for reduced memory and wireless datarate, or exploiting circuits with run-time scalable energy-quality degradation to meet the time-varying accuracy requirement at minimum energy).
The lectures are organized in a case-study fashion for immediate fruition, enabling the usage of design techniques and abstractions in practical cases, and bridging the gap between design principles and applications. The course covers the analysis of on-going and emerging technology trends in energy-constrained integrated systems, the fundamental design tradeoffs, and the design methodologies to manage such tradeoffs. Context-aware techniques for power management, wireless communications, sensor interfaces and processing are presented, where the signal and event pattern specificity are leveraged to reduce the energy at both circuit and system level. Energy-efficient on-chip sensor data sensemaking is also addressed from the perspective of signal processing and machine learning engines for detection/classification. Finally, several case studies are comparatively analyzed to link general design principles to silicon demonstrations, highlighting the “big ideas” that are (and will be) driving further advances in energy-constrained systems.

Talk by Prof. Makoto Nagata (Kobe University - Japan) - 21 September 2018

posted Sep 18, 2018, 6:52 PM by Massimo Alioto

Prof. Makoto Nagata (Kobe University - Japan) will give an exciting talk on "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security". The talk will take place on September 21, 2018 as follows:

TOPIC: Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security
SPEAKER: Prof. Makoto Nagata, Kobe University
DATE: 21 September 2018, Friday
TIME: 4pm to 5pm
VENUE: E1-06-03, Engineering Block E1, Faculty of Engineering, NUS         

All interested researchers, students and designers from industry are more than welcome to join.
The details on the logistics and the talks are also provided in the attached flyer.

Seminar by Prof. Alberto Sangiovanni-Vincentelli (UCBerkeley) - May 17, 2018

posted May 10, 2018, 3:44 AM by Massimo Alioto

Prof. Alberto Sangiovanni-Vincentelli (University of California, Berkeley) will give a talk on "LET'S GET PHYSICAL: ADDING PHYSICAL DIMENSIONS TO CYBER SYSTEMS". The talk will take place on May 17, 2018 at 12-1PM in E5-03-20.
All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS.
The details on the logistics and the talks are provided in the following.

SPEAKER: Prof. Alberto Sangiovanni-Vincentelli - University of California, Berkeley, USA
DATE: 17 May 2018, Thursday
TIME: 12pm to 1pm
VENUE: E5-03-20, Engineering Block E3, Faculty of Engineering, NUS 

ABSTRACT: Technology advances are creating major shifts in the industrial landscape. Traditional sectors such as transportation, medical and avionics, are witnessing fundamental changes in the supply chain and in the content where the interactions between the physical world and the computing world are becoming increasingly tight. Cyber Physical Systems, Systems of Systems, Internet of Things, Industrie 4.0, Swarm Systems and The Fog are all sectors that attract massive attention from the research communities and massive investment from industry. These concepts are tightly intertwined and describe a movement towards a fully interconnected planet where billions of devices interact via a complex mesh of wireless and wired communication infrastructures. The most compelling vision for the future of technology and industry is one where a swarm of devices is connected with the cloud to provide platforms for myriad of new applications. In this new world, new companies will arise and established ones will have to change radically their business model. The increasing sophistication and heterogeneity of these systems requires radical changes in the way sense-and-control platforms are designed to regulate them. 
In this presentation, I highlight the economic potential of CPS, their role in autonomous driving, and some of the design challenges due to the complexity, heterogeneity and power consumption of CPS.

Seminar by Prof. Jan Rabaey (UCBerkeley) - May 15, 2018

posted May 10, 2018, 3:43 AM by Massimo Alioto

Prof. Jan Rabaey (University of California, Berkeley) will give a talk on "Brain-like Cognitive Engineering Systems". The talk will take place on May 15, 2018 at 12-1PM in E3-06-01.
All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS.
The details on the logistics and the talks are provided in the following.

TOPIC: Brain-like Cognitive Engineering Systems
SPEAKER: Prof. Jan Rabaey - University of California, Berkeley, USA
DATE: 15 May 2018, Tuesday
TIME: 12pm to 1pm
VENUE: E3-06-01, Engineering Block E3, Faculty of Engineering, NUS       

Technology scaling and advancing device technologies have played a major role in making computational engines continuously more efficient. Yet that efficiency is still a couple of orders of magnitude away from what the human brain is capable of. Bridging that gap using traditional models and techniques is becoming increasingly harder due to implicit limitations and/or bounds in the devices, architectures and computational paradigms. The main question to ask is if computational techniques inspired by our current understanding of how the brain functions could help to overcome some if not most of these limitations. In this presentation we will explore a number of the properties of the brain function, and how these can/may map into the emerging nanotechnologies. Just to name a few: approximate pattern-based computation; close intertwining of logic and memory; 3D integration; learning-based programing model; sparsity and function-specific mapping. These observations will be illustrated with a set of concrete examples using a hyper-dimensional computing approach.

Seminar by Prof. Dennis Sylvester (Univ. Michigan) and Dr. Edith Beigné (CEA LETI) - April 4, 2018

posted Mar 19, 2018, 3:55 AM by Massimo Alioto

Prof. Dennis Sylvester (Univ. Michigan) and Dr. Edith Beigné will be the protagonists of the seminar session on "The future of pervasive sensing and computing - A vision from technology leaders". The session will take place on April 4, 2018 at 12-2PM in EA-06-05.
All interested researchers, students and designers from industry are more than welcome to join, here at ECE - NUS.
The details on the logistics and the talks are provided in the following.

TOPIC: Circuits and Systems for Ultra-Low Power mm-Scale Microsystems
SPEAKER: Prof Dennis Sylvester - University of Michigan, Ann Arbor, USA
DATE: 4 April 2018, Wednesday
TIME: 12pm to 1pm
VENUE: EA-06-05, Engineering Block EA, Faculty of Engineering, NUS       
ABSTRACT: This talk will describe recent progress at the University of Michigan in circuit building blocks for complete wireless sensing systems on the millimeter-scale. It will also highlight a few example systems, particularly focusing on applications in the audio space. Major circuit blocks that will be described include power management, low-power embedded non-volatile memories, hardware security primitives, and sensors and relevant interface circuits.
BIOGRAPHY: Dennis Sylvester is Professor of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. He received a PhD from the University of California, Berkeley and now is the Director of the Michigan Integrated Circuits Laboratory (MICL), a group of ten faculty and 70+ graduate students. He has held research staff positions in the Advanced Technology Group of Synopsys, Hewlett-Packard Laboratories, and visiting professorships at the National University of Singapore and Nanyang Technological University. He has published over 475 articles in his areas of interest, which include the design of millimeter-scale computing systems and energy efficient near-threshold computing.  He holds 40 US patents and serves as a consultant and technical advisory board member for electronic design automation and semiconductor firms in these areas.  He co-founded Ambiq Micro, a fabless semiconductor company developing ultra-low power mixed-signal solutions for compact wireless devices. He is an IEEE Fellow.

TOPIC: The future of low power circuits and embedded intelligence: emerging devices and new design paradigms
SPEAKER: Edith Beigné - Research Director of Integrated Circuits and System Division at CEA LETI
DATE: 4 April 2018, Wednesday
TIME: 1pm to 2pm
VENUE: EA-06-05, Engineering Block EA, Faculty of Engineering, NUS

ABSTRACT: Circuit and design division at CEA LETI is focusing on innovative architectures and circuits dedicated to digital, imagers, wireless, sensors, power management and embedded software. After a brief overview of adaptive circuits for low power multi-processors and IoT architectures, the talk will detail new technologies opportunities for more flexibility. Digital and mixed-signal architectures using 3D technologies will be presented in the scope of multi-processors activity as well as imagers and neuro-inspired circuits. Also, the integration of non-volatile memories will be shown in the perspective of new architectures for computing. Finally, embedding learning will be addressed to solve power challenges at the edge and in end-devices: some new design approaches will be discussed.
BIOGRAPHY: Edith Beigné joined CEA-LETI, Grenoble, France, in 1998. She is the Research Director of Integrated Circuits and System Division at CEA LETI. Since 2009, she has been a senior scientist in the digital and mixed-signal design lab where she researches low power and adaptive circuit techniques, exploiting asynchronous design and advanced technology nodes like FDSOI 28nm and 14nm for many different applications from high performance MPSoC to ultra-low power IoT applications. Her main research interests today are low power digital circuits, neuro-inspired architectures and 3D integration. She is part of ISSCC TPC since 2014 and part of VLSI’ symposium since 2015. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018.

IEEE JETCAS Special Issue on Energy-Quality Scalable Systems - Guest Editors: M. Alioto (NUS), V. De (Intel), A. Marongiu (ETHZ) - Paper submission now open

posted Sep 8, 2017, 10:41 PM by Massimo Alioto

The call for papers on "Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based" has just been released for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
Researchers are warmly invited to submit their paper contributions to be part of this highly impactful special issue in the area of energy-quality scalable sensing and computing, such as approximate sensing/computing, communication-inspired processing and learning-based systems that adapt the quality to the dataset, task, context and application, among the others.

Given its highly inter-disciplinary nature, contributions are welcome from authors working in the areas of circuits and systems, solid-state circuits, CAD, architectures, machine learning and signal processing (e.g., computer vision, audio). Please follow the instructions below, planning your submission to meet the deadline of Dec. 15, 2017.
For further information, you can contact Prof. Massimo Alioto.

View this email in your browser
Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based

Guest Editors

Massimo Alioto*, National University of Singapore,
Vivek De, Intel Labs,
Andrea Marongiu, ETH Zurich,
* corresponding Guest Editor

Scope and Purpose

The historical 100X/decade energy down-scaling is currently being threatened by the slowing down of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions and tradeoffs that enable further energy reductions need to be explored.

As design dimension to continue the exponential energy down-scaling, ample opportunities have been recently demonstrated in energy-quality (EQ) scalable circuits and systems, which dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Energy-quality scalable designs minimize energy at run time, based on the actual quality target that is set by the specific task, the context (e.g., recent events, power/energy availability), and the specific dataset at hand (e.g., more/less complex or noisy data). EQ scalable systems indeed reduce energy by treating quality as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. However, such “just-enough” or “on-demand” quality management cannot be pursued based on traditional metrics that are only vaguely related to quality, or are application unspecific (e.g., error rate).

Thanks to their inherent resiliency against noise/errors/inaccuracies/approximations and hence strong potential for EQ scaling, prominent examples of relevant applications are multimedia, motion sensing/wearables, smart bio-sensors, smart sensors for the Internet of Things (IoT), machine learning (e.g., deep learning), computer vision, audio processing, speech recognition, physical data aquisition/processing, data analytics, among many others. Being application-dependent, the quality is quantified differently in each application domain through well-established metrics, such as accuracy/sensitivity/specificity in machine learning, PSNR (or other perceptive metrics) in video processing, false alarm rate in IoT sensors, misclassification rate in signal classification, SNR in signal processing, mean error distance in approximate digital circuits, perplexity in unsupervised learning, entropy in random key generation, effective resolution in analog-to-digital conversion, tracking length in visual object tracking, missed event detection rate in implantables and bio-medical circuits, among the others. 

From the state of the art viewpoint, various concepts and demonstrations that save energy at degraded quality have been proposed within the general framework of EQ-scalable circuits and systems, and have been mostly focused on processing. Some examples are approximate computing (e.g., precision adjustment, gate pruning), communication-inspired approaches (e.g., algorithmic noise tolerance, voltage/frequency overscaling), stochastic and probabilistic computing (e.g., robabilistic CMOS, emerging devices), learning-based approaches (e.g., adaptation via background or foreground on-chip training). Furthermore, we are witnessing an interesting convergence of EQ scalable systems and machine learning, where the noise resilience and the learning ability of machine learning circuits/algorithms can be leveraged to achieve graceful quality degradation (i.e., wider opportunities for energy saving), and allow significant circuit/architectural simplifications and imperfections by compensation with on-chip training. Also, various demonstrations on EQ-scalable System on Chip (SoC) building blocks with substantial energy reductions have also been presented, such as memories, analog-to-digital converters, microprocessors, accelerators for vision, and engines for machine learning.

At this juncture, several challenges need to be addressed to extract the energy gains expected from EQ scaling, while systematically and efficiently design truly scalable systems. For example, new methods and techniques to inexpensively insert EQ knobs in all SoC components are needed, from analog and sensor interfaces to processing, power management, algorithms, and software. As other challenges, quality needs to be inexpensively sensed at low area and energy/power penalty, to retain the potential energy advantages offered by EQ scaling. Methods and techniques are also needed to make the quality degradation graceful, to extend the energy savings when operating at lower quality. Novel design paradigms and optimization methodologies are also needed to supervise the energy-quality control, based on an underlying application-to-hardware framework. Novel frameworks are also needed to make EQ scaling techniques more generally applicable (e.g., general-purpose platforms), spanning multiple levels of abstraction (e.g., circuit, architecture, algorithm, software) and sub-systems. In addition, innovative frameworks and techniques are needed to minimize the overall energy via true adaptation (e.g., on-chip learning), while keeping quality within bounds in a real-time and context-aware fashion. 

The above challenges require a highly inter-disciplinary collective effort, as they lie at the intersection of circuits and systems, solid-state circuits, CAD, architectures, machine learning, signal processing (e.g., computer vision, audio), and the related communities. Accordingly, the authors of this special issue will be invited to submit their paper contributions on the following and other topics related to energy-quality scalable systems: 
  • sensors and circuits (analog, digital, power management) with the capability to dynamically trade off energy and quality
  • lightweight methods for quality enhancement and graceful degradation, from circuits (e.g., variation-resilient design, intentional under-design), to architectures (e.g., approximate), algorithms (e.g., quality-aware termination of iterative algorithms), and systems (e.g., context-aware systems for relaxed quality requirement)
  • run-time quality sensing, control and adaptation at different levels of abstraction (e.g., circuit, architecture) and in different sub-systems (e.g., analog, digital, power management)
  • relaxed sensor and circuit design via compensation of non-idealities through off/on-chip learning
  • architecture/algorithm/software overdesign elimination through “just-enough” quality assurance
  • dynamically scalable approximate, communication-inspired, stochastic, learning-based circuits and systems
  • HW/SW co-design approaches to adaptively manage the energy-quality tradeoff
  • design methodologies, programming models, language abstractions and compiler support for structured and disciplined energy-quality scaling in computation, communication and data transfer, including quality control and recovery from over-approximation
  • quality-aware middleware at all processing layers, from low-level runtime to high-level scheduling
  • quality modeling, monitoring and run-time adaptation in general-purpose and application-specific hardware
  • approximate, communication-inspired and learning-based frameworks that adapt the quality to the dataset, task, context and application
  • innovative case studies and emerging applications leveraging energy-quality scaling, with significant time- and energy-to-solution reduction (e.g., machine learning).

Important Dates
  • Manuscript submissions due: December 15th, 2017
  • First round of reviews completed: February 15th, 2018
  • Notification to authors: February 22nd, 2018
  • Revised manuscript submissions due: March 22nd, 2018
  • Second round of reviews completed: May 15th, 2018
  • Notification of acceptance: June 15th, 2018
  • Final manuscripts due: July 1st, 2018
  • Target publication date: September 2018

Submission Guidelines

All submitted manuscripts must (i) conform to JETCAS formatting requirements and page-count limits (from 8 to 14 pages – see guidelines at; (ii) incorporate no less than 50% of new (previously unpublished) material; (iii) be submitted online at Please note that you need to select “Special Issue on Energy-Quality Scalable Circuits and Systems for Sensing and Computing” when you submit a manuscript to this journal issue.

Copyright © IEEE Circuits and Systems Society, All rights reserved

New Springer book edited by Prof. Alioto: first book on chip design for IoT, from circuits to systems

posted Dec 7, 2016, 5:08 PM by Massimo Alioto   [ updated Dec 7, 2016, 5:10 PM ]

The book "Enabling the Internet of Things - from Integrated Circuits to Integrated Systems" is being published by Springer and is now available at

This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. (...)

For further details, visit the above Springer webpage.

IEEE TCAS-I Special Issue on IoT (Guest Editors: M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli): paper submission now open

posted Aug 8, 2016, 1:23 AM by Massimo Alioto   [ updated Aug 8, 2016, 1:27 AM ]

The call for papers on "Circuits and Systems for the Internet of Things - From Sensing to Sensemaking" has just been released for the IEEE Trans. on Circuits and Systems - part I.
Researchers working in the space of the Internet of Things (IoT) are warmly invited to submit their paper contributions to be part of this highly impactful special issue.
The topic spans from sensing, to processing, to security and sensemaking (e.g., machine learning algorithms for on-chip knowledge extraction from sensed data). Emphasis is given to both "vertical" and "transversal" design methodologies and approaches that cross traditional design boundaries (see CfP below).

Please follow the instructions below, planning your submission to meet the deadline of Dec. 7, 2016.
For further information, you can contact Prof. Massimo Alioto.

TCAS I: Special Issue on CAS for the IoT - From Sensing to Sensemaking

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Call for Papers:
Special Issue on Circuits and Systems for the Internet of Things -
From Sensing to Sensemaking

The Internet of Things (IoT) is now at its onset as a result of a global effort to enable massively distributed integrated circuits and systems with sensing, processing, communication and energy management capabilities (the “IoTnodes”). The vision towards 1 Tera connected IoT nodes poses several challenges in the broad area of circuits and systems, including:
(i) the need for unprecedentedly high energy efficiency and low standby power,
(ii) ultra-low voltage operation and inexpensive resiliency-enhancement techniques,
(iii) very low cost across the entire chain from design to verification, and manufacturing,
(iv) systematic over-design margin elimination from the circuit to the application level,
(v) cyber-security assurance down to single chip level despite highly-constrained resources,
(vi) the need for early extraction of essential information from physical data within the IoT nodes themselves, to enable distributed learning/sensemaking and hence true IoT scalability.

Due to the gargantuan scale of the IoT, the above challenges need to be addressed through holistic approaches that embrace multiple levels of abstraction (verticality) and building blocks of the on-chip sensing/sensemaking chain (transversality). Nowadays, vertical approaches are progressively becoming more customary to exceed the artificial boundaries created by levels of abstraction, and enable advances that transcend their traditional limits. On the other hand, more research is needed to devise transversal methods that leverage the interaction within the sensing/sensemaking chain, from analog interfaces to processing, power delivery, wireless communications and HW/SW-level information security, while expanding into systems, data representation and algorithmic frameworks.

Authors are invited to submit Regular papers following the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) guidelines, within the remit of this Special Issue call. Topics within the remit of circuits and systems for IoTinclude (but are not limited to):

  • Circuit and system techniques for energy harvesting/delivery/management and tight coupling with analog/processing/communication sub-systems
  • Circuits and systems for ultra-low voltage, energy and standby power consumption
  • Adaptive and resilient analog and digital techniques for inexpensive counteraction of process/voltage/temperature variations
  • Highly power-efficient circuits for wireless communications in IoT
  • Energy-quality scalable and approximate circuits and systems for IoT
  • Heterogeneous, reconfigurable and other IoT-specific architectures
  • Circuit/architecture/system/algorithmic “just-enough” methods for over-design margin elimination at all levels of abstraction through adaptation to application, context, workload and dataset
  • Hardware-level security for IoT, from lightweight encryption to “physically unclonable functions” for chip authentication
  • System-on-chip design and verification methodologies for IoT
  • Circuit and system approaches and implications on data representation and algorithms for IoT
  • Circuits, systems and methods for on-chip machine learning and inference
  • Emerging technologies for IoT

Submission Guidelines
All submitted manuscripts must
(i) conform to TCAS-I’s formatting requirements and page-count limit (at no more than 14 pages);
(ii) incorporate no less than 50% of new (previously unpublished) material;
(iii) be submitted online at

Please note that you need to select “Special Issue on IoT” when you submit a manuscript to this Special Issue.

Paper Submission:  December 7, 2016
Completion of First Review:  February 7, 2017
Completion of Final Review: April 7, 2017
Target Publication: June 2017

Guest Editors
Prof. Massimo Alioto
National University of Singapore (Singapore)
Prof. Edgar Sanchez-Sinencio
Texas A&M University (USA)
Prof. Alberto Sangiovanni-Vincentelli
University of California at Berkeley (USA)



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Seminar on sub-10nm CMOS device-circuit interaction by Prof. Kaushik Roy (Purdue) - March 29, 2016

posted Mar 27, 2016, 6:30 PM by Massimo Alioto

DATE: 12-1:30PM on March 29, 2016        LOCATION: E1-06-09 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Device-Circuit Co-design of Multi-Gate FETs in Scaled Technologies


Sub-10nm FinFET scaling presents new challenges for technology and system designers. Leakage mechanisms such as direct source to drain tunneling (DSDT) through the channel barrier, which was uncommon in longer channel bulk MOSFETs, will start dominating for sub-10nm gate lengths, necessitating careful device design using quantum mechanical simulations. We analyze the impact of DSDT in underlapped/asymmetrically doped FinFETs using 2D ballistic Physics based simulations. The increase in the effective channel length resulting from using underlap leads to significant reduction in DSDT especially in nFinFETs where the majority carriers have a lower tunneling effective mass. By including the important leakage components such as DSDT, sub-threshold leakage and direct gate oxide tunneling in the device characteristics, we derive a compact model suitable for cell library characterization and synthesize a LEON3 microprocessor and a memory subsystem. Our system level simulation results suggest that overall power consumption in sub-10nm technologies will be dominated by DSDT. We also estimate the improvements possible by using fin thickness control as a means to overcome the on-current degradation arising from gate-underlap. Finally I will discuss device and circuit design issues related to steep slope tunnel FETs.

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Seminar on many-core energy-efficient architectures by Prof. Bevan Baas (UCDavis) - March 24, 2016

posted Mar 27, 2016, 6:17 PM by Massimo Alioto   [ updated Mar 27, 2016, 6:22 PM ]

DATE: 12-1:30PM on March 24, 2016        LOCATION: E1-06-05 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: A case for fine-grain processor arrays for efficient and high-performance computation


The continually-growing number of devices available per chip assures the presence of many processing blocks per die communicating by some type of inter-processor interconnect. It is interesting to consider what the granularity of the processing blocks should be given a fixed amount of die area. Between the domains of FPGAs and traditional processors lies a lightly-explored regime which we call fine-grain many-core, whose processors: can be programmed by simple C programs; typically operate with high throughput and high energy-efficiency; are well suited for deep submicron fabrication technologies; and are well matched to many DSP, multimedia, and embedded workloads, and—somewhat counterintuitively—also to some enterprise and scientific kernels.

The AsAP architecture is a fine-grain many-core system composed of a large number of programmable reduced-complexity processing elements with virtually no algorithm-specific hardware and with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS). Oscillators fully halt when there is no work to do, and restart at full speed in less than one cycle after work becomes available. Processors communicate through a reconfigurable full-rate circuit-switched mesh network and the third generation design includes a complementary very-small-area packet router.

An overview will be given of a fully-functional 36-processor chip and a 167-processor 1.2 GHz 65 nm chip with per-core dynamic supply voltage and dynamic clock frequency capabilities. Due to the MIMD architecture and individual near-optimal oscillator halting, the system operates with an energy per operation of 9.2 W at 1 trillion instructions/sec virtually independent of the system load. Several dozen kernels and applications have been coded with power, throughput, and area results comparing very well with solutions on available programmable processors. A simple C compiler and automatic mapping tool greatly simplify programming. A sneak preview of a third generation deep-submicron chip now being tested concludes the talk.


Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now a Professor.

Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, the Best Paper Award at the IEEE Intl Conference on Computer Design in 2011, Best Student Paper Award 3rd place at IEEE Intl MSCS 2015 and IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at DAC 2010, several Best Paper nominations, and he supervised the research that earned the College of Engineering Best Doctoral Dissertation Award Honorable Mention in 2013. From 2007-2012 he was an Associate Editor for the IEEE Journal of Solid-State Circuits. He has Co-Chaired and served on numerous conference program committees and has served as Guest Editor of several special issues.

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