News
New Springer book edited by Prof. Alioto: first book on chip design for IoT, from circuits to systems
The book "Enabling the Internet of Things - from Integrated Circuits to Integrated Systems" is being published by Springer and is now available at This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. (...) For further details, visit the above Springer webpage.  |
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IEEE TCAS-I Special Issue on IoT (Guest Editors: M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli): paper submission now open
The call for papers on "Circuits and Systems for the Internet of Things - From Sensing to Sensemaking" has just been released for the IEEE Trans. on Circuits and Systems - part I. Researchers working in the space of the Internet of Things (IoT) are warmly invited to submit their paper contributions to be part of this highly impactful special issue. The topic spans from sensing, to processing, to security and sensemaking (e.g., machine learning algorithms for on-chip knowledge extraction from sensed data). Emphasis is given to both "vertical" and "transversal" design methodologies and approaches that cross traditional design boundaries (see CfP below). Please follow the instructions below, planning your submission to meet the deadline of Dec. 7, 2016.
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Seminar on sub-10nm CMOS device-circuit interaction by Prof. Kaushik Roy (Purdue) - March 29, 2016
DATE: 12-1:30PM on March 29, 2016 LOCATION: E1-06-09 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: Device-Circuit Co-design of Multi-Gate FETs in Scaled Technologies  ABSTRACT Sub-10nm FinFET scaling presents new challenges for technology and system designers. Leakage mechanisms such as direct source to drain tunneling (DSDT) through the channel barrier, which was uncommon in longer channel bulk MOSFETs, will start dominating for sub-10nm gate lengths, necessitating careful device design using quantum mechanical simulations. We analyze the impact of DSDT in underlapped/asymmetrically doped FinFETs using 2D ballistic Physics based simulations. The increase in the effective channel length resulting from using underlap leads to significant reduction in DSDT especially in nFinFETs where the majority carriers have a lower tunneling effective mass. By including the important leakage components such as DSDT, sub-threshold leakage and direct gate oxide tunneling in the device characteristics, we derive a compact model suitable for cell library characterization and synthesize a LEON3 microprocessor and a memory subsystem. Our system level simulation results suggest that overall power consumption in sub-10nm technologies will be dominated by DSDT. We also estimate the improvements possible by using fin thickness control as a means to overcome the on-current degradation arising from gate-underlap. Finally I will discuss device and circuit design issues related to steep slope tunnel FETs. SHORT BIO Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE. |
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flyer_Prof. Roy.pdf
Seminar on many-core energy-efficient architectures by Prof. Bevan Baas (UCDavis) - March 24, 2016
DATE: 12-1:30PM on March 24, 2016 LOCATION: E1-06-05 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: A case for fine-grain processor arrays for efficient and high-performance computation  The continually-growing number of devices available per chip assures the presence of many processing blocks per die communicating by some type of inter-processor interconnect. It is interesting to consider what the granularity of the processing blocks should be given a fixed amount of die area. Between the domains of FPGAs and traditional processors lies a lightly-explored regime which we call fine-grain many-core, whose processors: can be programmed by simple C programs; typically operate with high throughput and high energy-efficiency; are well suited for deep submicron fabrication technologies; and are well matched to many DSP, multimedia, and embedded workloads, and—somewhat counterintuitively—also to some enterprise and scientific kernels. The AsAP architecture is a fine-grain many-core system composed of a large number of programmable reduced-complexity processing elements with virtually no algorithm-specific hardware and with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS). Oscillators fully halt when there is no work to do, and restart at full speed in less than one cycle after work becomes available. Processors communicate through a reconfigurable full-rate circuit-switched mesh network and the third generation design includes a complementary very-small-area packet router. An overview will be given of a fully-functional 36-processor chip and a 167-processor 1.2 GHz 65 nm chip with per-core dynamic supply voltage and dynamic clock frequency capabilities. Due to the MIMD architecture and individual near-optimal oscillator halting, the system operates with an energy per operation of 9.2 W at 1 trillion instructions/sec virtually independent of the system load. Several dozen kernels and applications have been coded with power, throughput, and area results comparing very well with solutions on available programmable processors. A simple C compiler and automatic mapping tool greatly simplify programming. A sneak preview of a third generation deep-submicron chip now being tested concludes the talk. SHORT BIO Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now a Professor. Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, the Best Paper Award at the IEEE Intl Conference on Computer Design in 2011, Best Student Paper Award 3rd place at IEEE Intl MSCS 2015 and IEEE Asilomar 2014, "WACIest" Best-In-Session Paper at DAC 2010, several Best Paper nominations, and he supervised the research that earned the College of Engineering Best Doctoral Dissertation Award Honorable Mention in 2013. From 2007-2012 he was an Associate Editor for the IEEE Journal of Solid-State Circuits. He has Co-Chaired and served on numerous conference program committees and has served as Guest Editor of several special issues. |
Seminar on Carbon Nanotubes by Prof. Subhasish Mitra (Stanford) - June 26, 2015
DATE: 12-1:30PM June 26, 2015 LOCATION: E5-03-23 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: From Nanodevices to Nanosystems: Carbon Nanotube N3XT Information Technology  ABSTRACT Carbon Nanotube Field-Effect Transistors (CNFETs) can revolutionize the design of highly energy-efficient future electronic systems. Unfortunately, carbon nanotubes (CNTs) face major obstacles such as substantial imperfections and variations inherent to CNTs, and low CNFET current densities. A combination of CNFET circuit design and CNT processing techniques (the "imperfection-immune paradigm") overcomes these challenges to enable the experimental demonstration of the carbon nanotube computer, and, more generally, arbitrary CNFET digital systems. These are the first system-level demonstrations among promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems. We will also discuss new nanosystem architectures enabled by monolithic three-dimensional (3D) integration of CNFETs and emerging memories. Such fine-grained 3D integration allows for computation immersed in memory, and is key to achieving very high degrees of energy efficiency for emerging abundant-data applications. This research was performed at Stanford University in collaboration with Prof. H.-S. Philip Wong and several graduate students. SHORT BIO Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel. Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotube imperfection-immune digital VLSI, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide. Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, and the Intel Achievement Award, Intel’s highest corporate honor. He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology. |
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Prof. Subhasish Mitra - June 26.pdf
Seminar on Approximate Computing by Prof. Kaushik Roy (Purdue) - June 23, 2015
DATE: 2-3:30PM June 23, 2015 LOCATION: E5-03-23 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: Approximate Computing for Energy-efficient Error-resilient Multimedia Systems  ABSTRACT In today’s world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, mining and synthesis. These facts pose an interesting design challenge to process digital data in an energy-efficient manner while catering to desired user quality requirements. Most of these multimedia applications possess an inherent quality of "error"-resilience. This means that there is considerable room for allowing approximations in intermediate computations, as long as the final output meets the user quality requirements. This relaxation in "accuracy" can be used to simplify the complexity of computations at different levels of design abstraction, which directly helps in reducing the power consumption. At the algorithm and architecture levels, the computations can be divided into significant and non-significant. Significant computations have a greater impact on the overall output quality, compared to non-significant ones. Thus the underlying architecture can be modified to promote faster computation of significant components, thereby enabling voltage-scaling (at the same operating frequency). At the logic and circuit levels, one can relax Boolean equivalence to reduce the number of transistors and decrease the overall switched capacitance. This can be done in a controlled manner to introduce limited approximations in common mathematical operations like addition and multiplication. All these techniques can be classified under the general topic of “Approximate Computing”, which is the main focus of this talk. SHORT BIO Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE. |
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Prof. Kaushik Roy - June 23.pdf
Seminar on 3D systems by Prof. Yusuf Leblebici (EPFL) - Dec. 11, 2014
DATE: 1-2PM Dec. 11, 2014 LOCATION: E5-03-20 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: Design and Testing Strategies for Modular 3D-Multiprocessor / Memory Systems Integration Using Die-level TSV Technology  ABSTRACT This talk offers a broad overview on 3D integration technologies, and also provides some outline / insight concerning architectural design implications. An innovative modular 3D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by Through-Silicon-Vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3D Network-on-Chip (NoC), which can route packets in the vertical direction. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90nm CMOS process and stacked using an in-house, Via-Last Cu-TSV process. Test results show that the proposed 3D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gbps. The talk will also discuss high speed serial data transmission possibilities over TSVs and offer a systematic cost/benefit analysis of data serialization for processor/memory stacks. SHORT BIO Yusuf Leblebici (M'90-SM'98-F'09) received the B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, Istanbul, Turkey, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign (UIUC) , in 1990. Since 2002, he is a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of six textbooks, as well as more than 300 articles published in various journals and conferences. He is a Fellow of IEEE since 2010, and he has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011. |
New Springer book
The book "Flip-Flop Design in Nanometer CMOS" has been published by Springer and is now available at  |
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video of talk at HotChips 2014 on Internet of Things - state of the art and directions
Prof. Alioto's talk at HotChips 2014 summarizes the current state of the art and provides technology directions for ultra-low power VLSI design for the Internet of Things. The video is available at https://www.youtube.com/watch?v=3WDQepWIs9A#t=2974. |
Prof. Alioto's Vision on the Internet of Things featured in a PCWorld article (Aug. 10, 2014)
The vision of Prof. Alioto on the Internet of Things has been featured in the PC World magazine, which is a popular global publication and the largest-circulation computing magazine in the world with millions of readers. The article can be found at http://www.pcworld.com/article/2463500/energy-harvested-from-body-environment-could-power-wearables-iot-devices.html. |
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