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ISSCC 2014 paper in collaboration with University of Michigan, Ann Arbor

posted Mar 9, 2014, 8:16 PM by Massimo Alioto
Collaboration with Prof. David Blaauw and Prof. Dennis Sylvester (Umich) led to the work that we presented at ISSCC 2014.
Our 28-nm chip demonstrates the absolutely first SRAM that can flexibly operate in error-free (traditional) or error-tolerant (errors occur, although in a controlled way) mode with dynamic and wide adjustment of the energy-quality tradeoff. This is a major step forward, towards our vision of processing platforms that embrace variations and their resulting faults, rather than overconstraining the design. The resulting energy can be significantly reduced whenever lower quality is tolerable, depending on the usage model and application/user's instantaneous requirements.

To probe further:
F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, San Francisco (CA), Feb. 2014

A voltage-scaled SRAM targeting both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, ECC and write assist, are selectively applied to bit positions with larger quality impact while performing voltage scaling to improve energy efficiency. A 28nm CMOS 32kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220mV below a baseline SRAM with 2% area penalty.