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Seminar on 3D systems by Prof. Yusuf Leblebici (EPFL) - Dec. 11, 2014

posted Dec 6, 2014, 9:18 AM by Massimo Alioto
DATE: 1-2PM Dec. 11, 2014        LOCATION: E5-03-20 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Design and Testing Strategies for Modular 3D-Multiprocessor / Memory Systems Integration Using Die-level TSV Technology

This talk offers a broad overview on 3D integration technologies, and also provides some outline / insight concerning architectural design implications. An innovative modular 3D stacked multi-processor architecture is presented.
The platform is composed of completely identical stacked dies connected together by Through-Silicon-Vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3D Network-on-Chip (NoC), which can route packets in the vertical direction. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90nm CMOS process and stacked using an in-house, Via-Last Cu-TSV process.
Test results show that the proposed 3D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gbps. The talk will also discuss high speed serial data transmission possibilities over TSVs and offer a systematic cost/benefit analysis of data serialization for processor/memory stacks.

Yusuf Leblebici (M'90-SM'98-F'09) received the B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, Istanbul, Turkey, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign (UIUC) , in 1990. Since 2002, he is a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis. He is the coauthor of six textbooks, as well as more than 300 articles published in various journals and conferences. He is a Fellow of IEEE since 2010, and he has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.