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Seminar on sub-10nm CMOS device-circuit interaction by Prof. Kaushik Roy (Purdue) - March 29, 2016

posted Mar 27, 2016, 6:30 PM by Massimo Alioto
DATE: 12-1:30PM on March 29, 2016        LOCATION: E1-06-09 (Engineering Blk E1, Faculty of Engineering, NUS) @ NUS campus (map)
TITLE: Device-Circuit Co-design of Multi-Gate FETs in Scaled Technologies


Sub-10nm FinFET scaling presents new challenges for technology and system designers. Leakage mechanisms such as direct source to drain tunneling (DSDT) through the channel barrier, which was uncommon in longer channel bulk MOSFETs, will start dominating for sub-10nm gate lengths, necessitating careful device design using quantum mechanical simulations. We analyze the impact of DSDT in underlapped/asymmetrically doped FinFETs using 2D ballistic Physics based simulations. The increase in the effective channel length resulting from using underlap leads to significant reduction in DSDT especially in nFinFETs where the majority carriers have a lower tunneling effective mass. By including the important leakage components such as DSDT, sub-threshold leakage and direct gate oxide tunneling in the device characteristics, we derive a compact model suitable for cell library characterization and synthesize a LEON3 microprocessor and a memory subsystem. Our system level simulation results suggest that overall power consumption in sub-10nm technologies will be dominated by DSDT. We also estimate the improvements possible by using fin thickness control as a means to overcome the on-current degradation arising from gate-underlap. Finally I will discuss device and circuit design issues related to steep slope tunnel FETs.

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 65 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD National Security Science and Engineering Faculty Fellow (2014-2019), and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.

Massimo Alioto,
Mar 27, 2016, 6:30 PM