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JSSC paper in collaboration with BWRC-UCBerkeley just accepted

posted Apr 17, 2013, 2:37 PM by Massimo Alioto   [ updated Apr 17, 2013, 2:49 PM ]
Collaboration with Prof. Jan Rabaey (UCBerkeley) leads to a new paper that will be published on the IEEE Journal of Solid-State Circuits on the August special issue.

To probe further:
Massimo Alioto, Elio Consoli, Jan Rabaey, "“EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions," in print on JSSC, Aug. 2013.

Abstract: A novel reconfigurable switched-capacitor “EChO” Power Management Unit is introduced for ultra-low power duty-cycled integrated systems (e.g., sensor nodes for critical event monitoring). “EChO” reduces the energy cost associated with sleep-to-active and active-to sleep transitions by 64% with an area overhead less than 1% and no impact on active mode operation. Analysis shows that approximately the same energy reduction is achieved over a very wide range of operating conditions and design constraints (e.g., ratio between flying and decoupling capacitances, granularity of the capacitor array). Measurements show 25-30% system power saving for a 65-nm testchip implementation of the “EChO” PMU powering a 16-kgate processing unit and a 2-kbit SRAM at 0.55-V voltage in active mode, assuming a 1-s wakeup cycle, 6.25-12.5% activity and a processing task of 250 cycles. The technique can be synergistically employed with traditional reconfiguration techniques that focus on efficiency in active mode (ignoring active-sleep transitions) to sum up the benefits.


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