Seminar on Approximate Computing by Prof. Kaushik Roy (Purdue) – June 23, 2015

DATE: 2-3:30PM June 23, 2015        LOCATION: E5-03-23 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map)TITLE: Approximate Computing for Energy-efficient Error-resilient Multimedia Systems ABSTRACTIn today’s world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, […]

Seminar on 3D systems by Prof. Yusuf Leblebici (EPFL) – Dec. 11, 2014

DATE: 1-2PM Dec. 11, 2014         LOCATION: E5-03-20 (Engineering Blk E5, Faculty of Engineering, NUS) @ NUS campus (map) TITLE: Design and Testing Strategies for Modular 3D-Multiprocessor / Memory Systems Integration Using Die-level TSV Technology ABSTRACT This talk offers a broad overview on 3D integration technologies, and also provides some outline / insight concerning architectural design implications. […]

New Springer book

The book “Flip-Flop Design in Nanometer CMOS” has been published by Springer and is now available at http://www.springer.com/engineering/circuits+%26+systems/book/978-3-319-01996-3

ISSCC 2014 paper in collaboration with University of Michigan, Ann Arbor

Collaboration with Prof. David Blaauw and Prof. Dennis Sylvester (Umich) led to the work that we presented at ISSCC 2014.Our 28-nm chip demonstrates the absolutely first SRAM that can flexibly operate in error-free (traditional) or error-tolerant (errors occur, although in a controlled way) mode with dynamic and wide adjustment of the energy-quality tradeoff. This is […]

IEEE TVLSI paper on the fastest/most energy efficient pulsed latch just accepted (in collaboration with BWRC-UCBerkeley)

Collaboration with Prof. Jan Rabaey (UCBerkeley) led to a new paper that will be published on the IEEE Transactions on VLSI Systems. To probe further: E. Consoli, G. Palumbo, J. Rabaey, M. Alioto, “A Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches,” in print on IEEE Trans. on VLSI Systems. Abstract: In this paper, […]

JSSC paper in collaboration with BWRC-UCBerkeley just accepted

Collaboration with Prof. Jan Rabaey (UCBerkeley) leads to a new paper that will be published on the IEEE Journal of Solid-State Circuits on the August special issue. To probe further: Massimo Alioto, Elio Consoli, Jan Rabaey, ““EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions,” in print on JSSC, Aug. 2013. Abstract: A novel reconfigurable switched-capacitor […]