Editorials
M. Alioto, “Opening of the 2023 Editorial Year – This Coda as Prelude of Next TVLSI Cycle with Sustained Growth,” IEEE Trans. on VLSI Systems, vol. 31, no. 1, pp. 1-2, Jan. 2023 (IEEE manuscript)
M. Alioto, “Editorial on the Opening of the 2022 TVLSI Editorial Year – Connecting Trends from Society to VLSI Systems,” IEEE Trans. on VLSI Systems, vol. 30, no. 1, pp. 1-2, Jan. 2022 (IEEE manuscript)
M. Alioto, “Second Quarter of the 2021 Editorial Year—A Year in Crescendo,” IEEE Trans. on VLSI Systems, vol. 29, no. 5, pp. 815-842, May 2021 (IEEE manuscript)
M. Alioto, “Opening of the 2021 Editorial Year – Overture for a New Year of Change,” IEEE Trans. on VLSI Systems, vol. 29, no. 1, pp. 1-2, Jan. 2021 (IEEE manuscript)
M. Alioto, “Editorial on the Conclusion of the 2020 Editorial Year – The Climactic Finale of a Peculiar Year,” IEEE Trans. on VLSI Systems, vol. 28, no. 12, pp. 1-2, Dec. 2020 (IEEE manuscript)
M. Alioto, “Editorial on the Opening of the New Editorial Year – The State of the Transactions on VLSI Systems,” IEEE Trans. on VLSI Systems, vol. 28, no. 1, pp. 1-2, Jan. 2020 (IEEE manuscript)
M. Alioto, “Editorial: TVLSI Keynote Papers Enriching Our Transactions with Invited Contributions,” IEEE Trans. on VLSI Systems, vol. 27, no. 7, p. 1485, July 2019 (IEEE manuscript)
M. Alioto, “Editorial on TVLSI Positioning—Continuing and Accelerating an Upward Trajectory,” IEEE Trans. on VLSI Systems, vol. 27, no. 2, pp. 253-280, Feb. 2019 (IEEE manuscript)
M. Alioto, V. De, A. Marongiu, Guest Editorial for the Special Issue on “Energy-Quality Scalable Circuits and Systems for Sensing and Computing: from Approximate, to Communication-Inspired and Learning-Based”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 361-368, Sept. 2018 (IEEE manuscript)
G. Di Capua, N. Horta, F. Fernandez, G. Dundar, S. Pennisi, G. Palumbo, M. Alioto, G. Giustolisi, Guest Editorial for the Special Issue on Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017, Elsevier INTEGRATION – The VLSI Journal, vol. 63, pp. 273-274, 2018
M. Alioto, E. Sanchez-Sinencio, A. Sangiovanni-Vincentelli, Guest Editorial for the Special Issue on Circuits and Systems for the Internet of Things – From Sensing to Sensemaking, IEEE Trans. on Circuits and Systems – part I, vol. 64, no. 9, pp. 2221-2225, Sept. 2017 (IEEE manuscript)
K. Chakrabarti, M. Alioto, Editorial on the First TVLSI Best AE and Reviewer Awards, IEEE Trans. on VLSI Systems, Aug. 2016 M. Alioto, Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing, IEEE Trans. on VLSI Systems, Aug. 2016 (IEEE manuscript)
M. Alioto, Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing, IEEE Trans. on Circuits and Systems – part II, vol. 59, no. 12, pp. 849-852, Dec. 2012 (IEEE manuscript)
Books or book chapters
L. Lin, S. Jain, K. Ali Ahmed, M. Alioto, Self-Powered Sensors for Next-Gen IoT – Everywhere, Always-on and Green, Springer, 2023 (Springer, Scholar Bank draft)
S. Taneja, M. Alioto, Immersed-in-Logic and In-Memory Primitives for Ubiquitous Hardware Security, Springer, 2023 (Springer, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling, Springer, 2020 (Springer, Scholar Bank draft)
M. Alioto (Ed.), Enabling the Internet of Things – from Integrated Circuits to Integrated Systems, Springer, 2017 (Springer, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, Flip-Flop Design in Nanometer CMOS – from High Speed to Low Energy, Springer, 2015 (Springer, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Design in the Energy-Delay Space,” (Chapter1) in Advanced Circuits for Emerging Technologies, Part I – Digital Design and Power Management, Wiley, March 2012 (Springer, Scholar Bank draft)
M. Alioto, G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), New York, Springer, 2005 (Springer, Scholar Bank draft)
International journals (2006-today)
J. Basu, L. Fassio, K. Ali, M. Alioto, “Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation,” accepted to IEEE Journal of Solid-State Circuits (invited), Jan. 2024 (IEEE manuscript, Scholar Bank draft)
H. Zhang, L. Lin, Q. Fang, M. Alioto, “Laser Voltage Probing Attack Detection with 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design” accepted to IEEE Journal of Solid-State Circuits (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation,” IEEE Trans. on Circuits and Systems – part I, vol. 70, no. 4, pp. 1439-1449, April 2023 (IEEE manuscript, Scholar Bank draft)
K. Ali, J. H. Teo, S. Sarkar, M. Alioto, “Dual-Mode Conversion Gating, Comparator Merging and Reference-Less Calibration for 2.7X Energy Reduction in SAR ADCs under Low-Activity Inputs,” in print on IEEE Solid-State Circuits Letters (IEEE manuscript, Scholar Bank draft)
L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “Voltage Reference with Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems down to 3.9 pW, 0.2 V,” in print on IEEE Access (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security – From Physical Design to Machine Learning-Based Hardware Patching,” in print on IEEE Open Journal of the Solid-State Circuits Society (IEEE manuscript, Scholar Bank draft)
T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, “STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks,” accepted to IEEE JETCAS (IEEE manuscript, Scholar Bank draft)
S. Taneja, V. Konandur Rajanna, M. Alioto, “In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security,” IEEE Journal of Solid-State Circuits (invited), vol. 57, no. 1, pp. 153-166, Jan. 2022 (IEEE manuscript, Scholar Bank draft)
U. De Alwis, M. Alioto, “TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference,” IEEE JETCAS, vol. 11, no. 4, pp. 620-633, Dec. 2021 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, “±CIM SRAM for Signed In-Memory Broad-Purpose Computing from DSP to Neural Processing,” IEEE Journal of Solid-State Circuits (invited), vol. 56, no. 10, pp. 2981-2992, Oct 2021 (IEEE manuscript, Scholar Bank draft)
P. Toledo, P. Crovetti, O. Aiello, M. Alioto, “Design of Digital OTAs with Operation down to 0.3 V and nW Power for Direct Harvesting,” IEEE Trans. On Circuits and Systems – part I, vol. 68, no. 9, pp. 3693-3706, Sept. 2021 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Fully-Synthesizable Unified True Random Number Generator and Cryptographic Core,” IEEE Journal of Solid-State Circuits (invited), vol. 56, no. 10, pp. 3049-3061, Oct. 2021 (IEEE manuscript, Scholar Bank draft)
P. Toledo, P. Crovetti, H. Klimach, S. Bampi, O. Aiello, M. Alioto, “A 300mV-Supply, sub-nW Power Digital-Based Operational Transconductance Amplifier,” IEEE Trans. on Circuits and Systems – part II, vol. 68, no. 9, pp. 3073-3077, Sept. 2021 (IEEE manuscript, Scholar Bank draft)
L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “A 0.6-to-1.8V Trimming-Less CMOS Current Reference with Near-100% Power Utilization,” IEEE Trans. on Circuits and Systems – part II, vol. 68, no. 9, pp. 3038-3042, Sept. 2021 (IEEE manuscript, Scholar Bank draft)
L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “Trimming-Less Voltage Reference for Highly-Uncertain Harvesting down to 0.25V, 5.4-pW,” IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3134-3144, Oct. 2021 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “From Less Batteries to Battery-Less Integrated Systems through Ultra-Wide Power-Performance Adaptation down to pWs,” IEEE Design&Test (invited), vol. 38, no. 5, pp. 90-133, Oct. 2021 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, P. Toledo, M. Alioto, “Rail-to-Rail Dynamic Voltage Comparator Scalable down to pW-Range Power and 0.15-V Supply,” vol. 68, no. 7, pp. 2675-2679, July 2021 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion,” IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2182-2192, July 2021 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Sub-nW Microcontroller with Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes,” IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1618-1629, May 2021 (IEEE manuscript, Scholar Bank draft)
P. Toledo, P. Crovetti, O. Aiello, M. Alioto, “Fully Digital Rail-to-Rail OTA with Sub-1,000 µm2 Area, 250-mV Minimum Supply and nW Power at 150-pF Load in 180nm,” IEEE Solid-State Circuits Letters, vol. 3, pp. 474-477, Sept. 2020 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, “Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads,” IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 394-397, Sept. 2020 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core,” IEEE Solid-State Circuits Letters (invited), vol. 3, pp. 402-405, Sept. 2020 (IEEE manuscript, Scholar Bank draft)
L. Fassio, F. Settino, L. Longyang, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “A Robust Sub-Threshold, Low Power-Delay, Energy and Area Efficient Level Shifter,” IEEE Trans. on Circuits and Circuits – part II, vol. 68, no. 4, pp. 1393-1397, April 2021 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, “Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies,” IEEE Journal of Solid-State Circuits (invited), vol. 55, no. 10, pp. 2670-2679, Oct. 2020 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, S. Perri, P. Corsonello, M. Alioto, “Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation,” IEEE Transactions on Circuits and Systems – part II, vol. 67, no. 12, pp. 3427-3431, Dec. 2020 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation,” IEEE Access, vol. 8, no. 1, pp. 70890 – 70899, April 2020 (IEEE manuscript, Scholar Bank draft)
A. Alvarez, G. Ponnusamy, M. Alioto, “Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision,” IEEE Access, vol. 8, pp. 18951-18961, Jan. 2020 (IEEE manuscript, Scholar Bank draft)
J. H. Teo, S. Cheng, M. Alioto, “Low-Energy Voice Activity Detection via Energy-Quality Scaling from Data Conversion to Machine Learning,” IEEE Trans. on CAS – part I, vol. 67, no. 4, pp. 1378-1377, April 2020 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Integrated Power Management for Battery-Indifferent Systems with Ultra-Wide Adaptation down to nW,” IEEE Journal of Solid-State Circuits (invited), vol. 55, no. 4, pp. 967-976, April 2020 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Longyang, M. Alioto, “Automated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling,” IEEE Trans. on VLSI Systems, vol. 28, no. 3, pp. 777-790, March 2020 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Reconfigurable Clock Networks for Wide Voltage Scaling,” IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2622-2631, Sept. 2019 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Standard Cell-Based Ultra-Compact DACs in 40nm CMOS,” IEEE Access, vol. 7, no. 1, pp. 126479-126488, Aug. 2019 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Trends in Hardware Security: from Basics to ASICs,” IEEE Solid-State Circuits Magazine (invited), vol. 11, no. 3, pp. 56-74, Aug. 2019 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable 12-bit, 500um2, 55kS/s DAC with Graceful Degradation and Dynamic Power-Resolution Scaling in 40nm,” IEEE Trans. on CAS – part I, vol. 66, no. 8, pp. 2865-2875, Aug. 2019 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, L. Lin, M. Alioto, “A pW-Power Hz-Range Oscillator Operating with a 0.3V-1.8V Unregulated Supply,” IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1487-1496, May 2019 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, S. Perri, P. Corsonello, M. Alioto, “Energy-Quality Scalable Adders Based on Non-Zeroing Bit Truncation,” IEEE Trans. on VLSI Systems, vol. 27, no. 4, pp. 964-968, April 2019 (IEEE manuscript, Scholar Bank draft)
M. N. Aman, S. Taneja, B. Sikdar, K. C. Chua, M. Alioto, “Token-Based Security for the Internet of Things with Dynamic Energy-Quality Tradeoff,” IEEE Internet of Things Journal, vol. 6, no. 2, pp. 2843-2859, Feb. 2019 (IEEE manuscript, Scholar Bank draft)
M. Alioto, V. De, A. Marongiu, “Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore’s Law,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 4, pp. 653-678, Dec. 2018 (IEEE manuscript, Scholar Bank draft)
S. Taneja, A. Alvarez, M. Alioto, “Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02fJ/b in 40nm,” IEEE Journal of Solid-State Circuits (invited), vol. 53, no. 10, pp. 2828-2839, Oct. 2018 (invited) (IEEE manuscript, Scholar Bank draft)
Q.-K. Trinh, S. Ruocco, M. Alioto, “Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories,” IEEE Trans. on CAS – part I, vol. 65, no. 10, pp. 3338-3348, Oct. 2018 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Longyang, M. Alioto, “Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures under Wide Voltage Scaling,” IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 632-641, Feb. 2018 (IEEE manuscript, Scholar Bank draft)
R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, “A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/MTJ Circuits,” IEEE Trans. on CAS – part I, vo. 65, no. 3, pp. 1086-1095, March 2018 (IEEE manuscript, Scholar Bank draft)
Q. K. Trinh, S. Ruocco, M. Alioto, “Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs,” IEEE Trans. on CAS – part I, vol. 65, no. 4, pp. 1269-1278, April 2018 (IEEE manuscript, Scholar Bank draft)
Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M Alioto, D. Blaauw, D. Sylvester, “iRazor: Current-Based Error Detection and Correction Scheme for PVT variation in 40-nm ARM Cortex-R4 Processor,” IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 619-631, Feb. 2018 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Shahghasemi, “The Internet of Things on Its Edge: Trends towards Its Tipping Point,” in print on the special issue on “Recent Advances on IoT-based Consumer Electronics”, IEEE Consumer Electronics Magazine (invited), vol. 7, no. 1, pp. 77-87, Jan. 2018 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, “Design-Oriented Energy Models for Wide Voltage Scaling down to the Minimum Energy Point,” IEEE Trans. on CAS – part I, vol. 64, no. 12, pp. 3115-3125, Dec. 2017 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Scotti, A. Trifiletti, “A Novel Framework to Estimate the Path Delay Variability on the Back of an Envelope via the Fan-Out-of-4 Metric,” IEEE Trans. on CAS – part I, vol. 64, no. 8, pp. 2073-2085, Aug. 2017 (IEEE manuscript, Scholar Bank draft)
K. T. Quang, S. Ruocco, M. Alioto, “Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read,” IEEE Trans. on CAS – part I, vol. 63, no. 10, pp. 1652-1660, Oct. 2016 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “Approximate SRAMs with Dynamic Energy-Quality Management,” IEEE Trans. on VLSI Systems, vol. 24, no. 6, pp. 2128-2141, June 2016 (IEEE manuscript, Scholar Bank draft)
A. Alvarez, W. Zhao, M. Alioto, “Static Physically Unclonable Functions for Secure Chip Identification with 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65nm,” IEEE Journal on Solid-State Circuits, vol. 51, no. 3, pp. 763-775, March 2016 (IEEE manuscript, Scholar Bank draft)
K. T. Quang, S. Ruocco, M. Alioto, “Voltage Scaled STT-MRAMs towards Minimum-Energy Write Access,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 305-318, Sept 2016 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “SRAM for Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 1310-1323, March 2015 (IEEE manuscript, Scholar Bank draft)
M. Alioto, Elio Consoli, G. Palumbo, “Variations in Nanometer CMOS Flip-Flops: Part II – Energy Variability and Impact of Other Sources of Variations,” IEEE Trans. on CAS – part I, vol. 62, n. 3, pp. 835-843, March 2015 (IEEE manuscript, Scholar Bank draft)
M. Alioto, Elio Consoli, G. Palumbo, “Variations in Nanometer CMOS Flip-Flops: Part I – Impact of Process Variations on Timing,” in print on IEEE Trans. on CAS – part I (IEEE manuscript, Scholar Bank draft)
M. Shoaran, A. Tajalli, M. Alioto, A. Schmid, Y. Leblebici, “Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits,” IEEE Trans. on CAS – part I, vol. 62, no. 2, pp. 458-467, Feb. 2015 (IEEE manuscript, Scholar Bank draft)
L. Freyman, D. Fick, M. Alioto, D. Blaauw, D. Sylvester, “A 346μm2 VCO-based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2462-2473, Nov. 2014 (IEEE manuscript, Scholar Bank draft)
L. Artola, G. Hubert, M. Alioto, “Comparative soft error evaluation of layout cells in FinFET technology,” in print on Microelectronics Reliability (Elsevier) (IEEE manuscript, Scholar Bank draft)
W. Zhao, Y. Ha, M. Alioto, “Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study,” in print on IEEE Trans. on VLSI Systems (IEEE manuscript, Scholar Bank draft)
M. Tache, V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, “Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates” Journal of Low Power Electronics, Vol. 10, N° 1, pp. 137-148, March 2014 (invited, special selection on the 4th European Workshop on CMOS Variability – VARI 2013).(IEEE manuscript, Scholar Bank draft)
M. Alioto, D. Esseni, “Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II – Evaluation at Circuit Level and Design Perspectives,” IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2499-2512, Dec. 2014 (IEEE manuscript, Scholar Bank draft)
D. Esseni, M. Guglielmini, B. Kapidani, T. Rollo, M. Alioto, “Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part I – Device-Circuit Interaction and Evaluation at Device Level,” IEEE Trans. on VLSI Systems, vol. 22, no. 12, pp. 2488-2498, Dec. 2014 (IEEE manuscript, Scholar Bank draft)
E. Consoli, G. Palumbo, J. Rabaey, M. Alioto, “A Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches,” IEEE Trans. on VLSI Systems, vol. 22, no. 7, pp. 1593-1605, July 2014 (IEEE manuscript, Scholar Bank draft)
M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, A. Trifiletti, “Effectiveness of Leakage Power Analysis attacks on DPA-resistant logic styles under process variations,” IEEE Trans. on Circuits and Systems – part I, vol. 61, no. 2, pp. 429-442, Feb. 2014 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, J. Rabaey, ““EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions,” IEEE Journal of Solid-State Circuits (invited), vol. 48, no. 8, pp. 1921-1932, Aug. 2013 (IEEE manuscript, Scholar Bank draft)
F. Crupi, D. Albano, M. Alioto, J. Franco, L. Selmi, J. Mitard, G. Groeseneken, “Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits,” IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 972-977, March 2013 (IEEE manuscript, Scholar Bank draft)
F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, G. Groeseneken, “Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements,” IEEE Trans. on Circuits and Systems – part II, vol. 59, no. 7, pp. 439-442, July 2012 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates,” IEEE Trans. on Circuits and Systems – part I, vol. 59, no. 10, pp. 2292-2300, Oct. 2012 (IEEE manuscript, Scholar Bank draft)
F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling,” IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1487-1495, Aug. 2012 (IEEE manuscript, Scholar Bank draft)
D. Baccarin, D. Esseni, M. Alioto, “Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks,” IEEE Trans. on VLSI Systems, vol. 20, no. 8, pp. 1467-1472, Aug. 2012 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, M. Alioto, P. Corsonello, “Tapered-Vth Approach for Energy-Efficient CMOS Buffers,” IEEE Trans. on Circuits and Systems – part I, vol. 58, no. 11, pp. 2698-2707, Nov. 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “From Energy-Delay Metrics to Constraints on the Design of Digital Circuits,” International Journal of Circuit Theory and Applications, vol. 40, no. 8, pp. 815-834, Aug. 2012 (Wiley manuscript, Scholar Bank draft)
M. Alioto, “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” IEEE Trans. on Circuits and Systems – part I (invited), vol. 59, no. 1, pp. 3-29, Jan. 2012 (IEEE manuscript, Scholar Bank draft)
M. Alioto, ”Modeling Strategies of the Input Admittance of RC Interconnects for VLSI CAD Tools,” Microelectronics Journal (Elsevier), vol. 42, no. 1, pp. 63-73, Jan. 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, G. Palumbo, “Optimized Design of Parallel Carry-Select Adders,” Integration – the VLSI Journal (Elsevier), vol. 44, no. 1, pp. 62-74, Jan. 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, S. Badel, Y. Leblebici, “Optimization of the Wire Grid Size for Differential Routing: Analysis and Impact on the Power-Delay-Area Tradeoff,” Microelectronics Journal (Elsevier), vol. 41, no. 10, pp. 669-679, Oct. 2010 (IEEE manuscript, Scholar Bank draft)
P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, ”Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements,” IEEE Trans. on VLSI Systems, vol. 19, no. 9, pp. 1569-1582, Sept. 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, ”Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells,” IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 751-762, May 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II – Results and Figures of Merit,” IEEE Trans. on VLSI Systems, vol. 19, no. 5, pp. 737-750, May 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, ”Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I – Methodology and Design Strategies,” IEEE Trans. on VLSI Systems, vo. 19, no. 5, pp. 725-736, May 2011 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “ Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1597-1607, July 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 7, pp. 1583-1596, July 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 6, pp. 1273-1286, June 2010 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy,” Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 879-895, 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Simple and Accurate Modeling of the Output Transition Time in Nanometer CMOS Gates,” International Journal of Circuit Theory and Applications, vol. 38, no. 10, pp. 995-1012 (Wiley manuscript, Scholar Bank draft)
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: a Novel Class of Attacks to Nanometer Cryptographic Circuits,” IEEE Trans. on Circuits and Systems – part I, vol. 57, no. 2, pp. 355-367, Feb. 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 697-710, May 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, “A general power model of Differential Power Analysis attacks to static logic circuits,” IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 711-724, May 2010 (IEEE manuscript, Scholar Bank draft)
A. Tajalli, M. Alioto, Y. Leblebici, “Improving power-delay performance of ultralow-power subthreshold SCL circuits,” IEEE Trans. on Circuits and Systems – part II, vol. 56, no. 2, pp. 127-131, Feb. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, “Differential Power Analysis Attacks to Precharged Busses: a General Analysis for Symmetric-Key Cryptographic Algorithms,” IEEE Trans. on Dependable and Secure Computing, vol. 7, no. 3, pp. 226-239, July-Sept. 2010 (IEEE manuscript, Scholar Bank draft)
M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, “Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology,” IEEE Trans. on VLSI Systems, vol.18, no.2, pp. 232-245, Feb. 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Analysis and Modeling of Energy Consumption in RLC Tree Circuits,” IEEE Trans. on VLSI Systems, vol. 17, no. 2, pp. 278-291, Feb. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Power-Aware Design of Nanometer MCML Tapered Buffers,” IEEE Trans. on Circuits and Systems – part II, vol. 55, no. 1, pp. 16-20, Jan. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders,” IEE Electronics letters, vol. 43, no. 13, pp. 707-709, 21st June 2007 (IEEE manuscript, Scholar Bank draft)
International conferences (2006-today)
A. Gupta, J. Vohra, M. Alioto, “CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm,” accepted to VLSI Symposium 2024, Honolulu (USA), June 2024
A. Gupta, J. Vohra, V. Konandur, M. Alioto, “122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm,” accepted to VLSI Symposium 2024, Honolulu (USA), June 2024
A. K. Gundu, L. Fassio, M. Alioto, “E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process,” accepted to VLSI Symposium 2024, Honolulu (USA), June 2024
J. Vohra, A. Gupta, M. Alioto, “Imager with In-Sensor Event Detection and Morphological Transformations with 2.9 pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40 nm,” accepted to ISSCC 2024, San Francisco (USA), Feb. 2024 (IEEE manuscript, Scholar Bank draft)
K. Ali Ahmed, R. Yang, P. Salamani, V. Rajanna, M. Alioto, “Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 µW Peak Power for Purely-Harvested Green Systems,” in Proc. of ESSCIRC 2023, Lisbon (Portugal), Sept. 2023 (IEEE manuscript, Scholar Bank draft)
J. Vohra, K. Ali Ahmed, M. Alioto, “A 0.4-V 12-bit Self-Calibrated SAR ADC with Offset Injection Assist Achieving 0.43 fJ/conv-step,“ in Proc. of ESSCIRC 2023, Lisbon (Portugal), Sept. 2023 (IEEE manuscript, Scholar Bank draft)
A. Gupta, S. Kumar, V. Konandur, S. Taneja, M. Alioto, “Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
J. Basu, L. Fassio, K. Ali, M. Alioto, “Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
L. Fassio, O. Aiello, M. Alioto, “38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
Q. Fang, L. Lin, H. Zhang, T. Wang, M. Alioto, “Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
H. Zhang, L. Lin, Q. Fang, U. S. H. Kalingage, M. Alioto, “Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
J. Basu, Sachin Taneja, V. Konandur Rajanna, T. Wang, M. Alioto, “ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm,” in Proc. of VLSI Symposium 2023, Kyoto (Japan), June 2023 (IEEE manuscript, Scholar Bank draft)
U. De Alwis, X. Zhongheng, M. Alioto, “Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes,” accepted to IEEE AICAS 2023 (IEEE manuscript, Scholar Bank draft)
K. A. Ahmed, H. Okuhara, M. Alioto, “55-pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely-Harvested Sensor Nodes,” accepted to IEEE ISSCC 2023 (IEEE manuscript, Scholar Bank draft)
U. De Alwis, M. Alioto, “Architecture for 3D Convolutional Neural Networks Based on Temporal Similarity Removal,” accepted to IEEE ICECS 2022 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs,” in Proc. of IEEE ESSCIRC 2022 (invited), Milan (Italy), pp. 33-40, Sept. 2022 (IEEE manuscript, Scholar Bank draft)
O. Aiello, M. Alioto, “Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting,” accepted to IEEE ESSCIRC 2022 (IEEE manuscript, Scholar Bank draft)
H. Zhang, L. Lin, Q. Fang, M. Alioto, “On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design,” accepted to IEEE VLSI Symposium 2022 (IEEE manuscript, Scholar Bank draft)
K. Ahmed, L. Lin, P. Salamani, M. Alioto, “Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-µW Peak Power in Purely-Harvested Systems,” accepted to IEEE VLSI Symposium 2022 (IEEE manuscript, Scholar Bank draft)
V. Konandur, H. Raghav, T. Wang, M. Alioto, “Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks,” accepted to IEEE VLSI Symposium 2022 (IEEE manuscript, Scholar Bank draft)
A. Gupta, V. Konandur, T. Salam, S. Jain, O. Aiello, P. Crovetti, M. Alioto, “DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm,” accepted to IEEE CICC 2022 (IEEE manuscript, Scholar Bank draft)
U. De Alwis, M. Alioto, “Temporal Redundancy-Based Computation Reduction for 3D Convolutional Neural Networks,” accepted to IEEE AICAS 2022 (IEEE manuscript, Scholar Bank draft)
Q. Fang, L. Lin, Y. Z. Wong, H. Zhang, M. Alioto, “Side-Channel Attack Counteraction via Machine Learning Targeted Power Compensation for Post-Silicon HW Security Patching,” accepted to IEEE ISSCC 2022 (IEEE manuscript, Scholar Bank draft)
Q. Fang, M. Alioto, “Last-round and Joint First/Last-Round Power Analysis Attacks on PRESENT,” accepted to IEEE AsianHOST 2021 (IEEE manuscript, Scholar Bank draft)
S. Wu, K. De Silva, S. Gutgutia, B. Baas, M. Alioto, “A 1448-Mpixel/s, 84-pJ/pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution,” in Proc. of IEEE ASSCC 2021, Busan (Korea), Nov 2021 (IEEE manuscript, Scholar Bank draft)
L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “A 0.6-to-1.8V Trimming-Less CMOS Current Reference with Near-100% Power Utilization,” accepted to IEEE ISICAS2021 (IEEE manuscript, Scholar Bank draft)
P. Toledo, P. Crovetti, H. Klimach, S. Bampi, O. Aiello, M. Alioto, “A 300mV-Supply, sub-nW Power Digital-Based Operational Transconductance Amplifier,” accepted to IEEE ISICAS2021 (IEEE manuscript, Scholar Bank draft)
V. Konandur Rajanna, S. Taneja, M. Alioto, “A 109TOPS/mm2 and 749-1,459TOPS/W SRAM Buffer with In-Memory Inference and Prediction-Less Bitline Activity Reduction in 28nm,” accepted to IEEE ESSCIRC 2021 ((IEEE manuscript, Scholar Bank draft)
L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “Trimming-Less 0.2-V, 3.2-pW Voltage Reference Based on Corner-Aware Replica Combination with 1.6% Process Sensitivity, 1.4-mV Accuracy across PVT and Wafers,” accepted to IEEE ESSCIRC 2021 (IEEE manuscript, Scholar Bank draft)
L. Lin, K. Ali Ahmed, P. S. Salamani, M. Alioto, “Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-µW Peak Power Envelope,” IEEE VLSI Symposium 2021, Kyoto (Japan), June 2021 (IEEE manuscript, Scholar Bank draft)
P. Agarwal, V. Konandur Rajanna, W. D. Toh, B. C. K. Tee, M. Alioto, “Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density,” IEEE VLSI Symposium 2021, Kyoto (Japan), June 2021 (IEEE manuscript, Scholar Bank draft)
U. De Alwis, M. Alioto, “TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead,” accepted to IEEE AICAS 2021 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Unified In-Memory Dynamic (TRNG) and Multi-Bit Static (PUF) Entropy Generation for Ubiquitous Hardware Security,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2021, pp. 498-499 (IEEE manuscript, Scholar Bank draft)
T.-N. Pham, Q.-K. Trinh, I.-J. Chang, M. Alioto, “STT-BNN: A Novel Energy-efficient and Scalable BNN Accelerator Based on STT-MRAM,” accepted to IEEE ISCAS 2021 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2021, pp. 74-75 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization in a Cryptographic Core for Constrained Secure Systems,” in Proc. of IEEE ASSCC 2020, Nov. 2020 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Lin, M. Alioto, “Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads Based on Commercial Bitcell,” in Proc. of IEEE ASSCC 2020, Nov. 2020 (IEEE manuscript, Scholar Bank draft)
J. H. Teo, K. Ali, M. Alioto, “Voice Activity Detection with >83% Accuracy under SNR down to -3dB at 1.19µW and 0.07mm2 in 40nm,” in Proc. of IEEE ASSCC 2020, Nov. 2020 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting,” in Proc. of VLSI Symposium 2020, Honolulu (USA), June 2020 (IEEE manuscript, Scholar Bank draft)
Luigi Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “A 0.25-V, 5.3-pW Voltage Reference with 25-µV/oC Temperature Coefficient, 140-µV/V Line Sensitivity and 2,200-µm2 Area in 180nm,” in Proc. of VLSI Symposium 2020, Honolulu (USA), June 2020 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Deep Sub-pJ/bit Low-Area Energy-Security Scalable SIMON Crypto-Core,” in Proc. of ISCAS 2020, Seville (Spain), Oct 2020 (IEEE manuscript, Scholar Bank draft)
S. Jain, L. Longyang, M. Alioto, “Low-Overhead Drop-In Techniques to Extend the Energy-Performance Tradeoff in Microcontrollers Beyond VDD Scaling,” in Proc. of ASSCC 2019, pp. 125-129, Macau (China), Nov. 2019 (IEEE manuscript, Scholar Bank draft)
J. H. Teo, S. Cheng, M. Alioto, “Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector,” in Proc. of ICECS 2019, pp. 174-177, Genoa (Italy), Nov. 2019 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, A. Sharma, M. Alioto, “Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort,” in Proc. of ICECS 2019, pp. 715-718, Genoa (Italy), Nov. 2019 (IEEE manuscript, Scholar Bank draft)
M. Lanuzza, R. De Rose, F. Crupi, M. Alioto, “An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops,” in Proc. of ICECS 2019, pp. 158-161, Genoa (Italy), Nov. 2019 (IEEE manuscript, Scholar Bank draft)
S. Taneja, M. Alioto, “Physically Unclonable Function Design Margin Reduction via In-Situ and PVT Sensor Fusion,” in Proc. of ESSCIRC 2019, pp. 61-64, Krakow (Poland), Oct 2019 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW,” VLSI Symposium 2019, Kyoto (Japan), pp. C178-179, June 2019 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic,” in Proc. of IEEE ISCAS 2019, Sapporo (Japan), May 2019 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, P. Corsonello, S. Perri, M. Alioto, “Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation,” in Proc. of IEEE ISCAS 2019, Sapporo (Japan), May 2019 (IEEE manuscript, Scholar Bank draft)
M. Alioto, S. Taneja, “Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems,” in Proc. of IEEE CICC 2019 (invited), Austin (USA), April 2019 (IEEE manuscript, Scholar Bank draft)
V. Konandur, M. Alioto, “Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications,” in Proc. of IEEE CICC 2019, Austin (USA), April 2019 (IEEE manuscript, Scholar Bank draft)
S. Wu, S. Gutgutia, M. Alioto, B. Baas, “Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,” accepted to Asilomar 2018 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “A Sub‐Leakage pW‐Power Hz Range Relaxation Oscillator Operating with 0.3V‐1.8V Unregulated Supply,” 2018 VLSI Symposium on VLSI Circuits Digest of Technical Papers, C11-4, Honolulu (USA), June 2018 (IEEE manuscript, Scholar Bank draft)
S. Wu, S. Gutgutia, M. Alioto, B. Baas, “Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding,” accepted to Asilomar 2018 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “A 595pW 14pJ/cycle Microcontroller with Dual-mode Standard Cells and Self-startup for Battery-Indifferent Distributed Sensing,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2018, pp. 44-45 (IEEE manuscript, Scholar Bank draft)
Q. K. Trinh, S. Ruocco, M. Alioto, “Novel Time-Based Sensing Scheme for STT-MRAMs,” in Proc. of ISCAS 2018, pp. 1151-1154, Florence (Italy), May 2018 (IEEE manuscript, Scholar Bank draft)
G. Santoro, M. R. Casu, V. Peluso, A. Calimera, M. Alioto, “Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS,” in Proc. of ISCAS 2018, pp. 1151-1154, Florence (Italy), May 2018 (IEEE manuscript, Scholar Bank draft)
O. Aiello, P. Crovetti, M. Alioto, “Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V,” in Proc. of ISCAS 2018, Florence (Italy), May 2018 (IEEE manuscript, Scholar Bank draft)
G. Santoro, M. R. Casu, V. Peluso, A. Calimera, M. Alioto, “Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator,” in Proc. of DATE 2018, pp. 1151-1154, Dresden (Germany), March 2018 (IEEE manuscript, Scholar Bank draft)
A. Alvarez, G. Ponnusamy, M. Alioto, “EQSCALE: Energy-Quality Scalable Feature Extraction Engine for Sub-mW Real-time Video Processing with 0.55 mm2 Area in 40nm CMOS,” in Proc. of ASSCC 2017, pp. 241-244 , Seoul (Korea), Nov. 2017 (IEEE manuscript, Scholar Bank draft)
S. Taneja, A. Alvarez, G. Sadagopan, M. Alioto, “A Fully-Synthesizable C-Element Based PUF Featuring Temperature Variation Compensation with Native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm,” in Proc. of ASSCC 2017, pp. 301-304, Seoul (Korea), Nov. 2017 (IEEE manuscript, Scholar Bank draft)
L. Lin, S. Jain, M. Alioto, “Reconfigurable Clock Networks for Random Skew Mitigation from Sub-Threshold to Nominal Voltage,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 440-441 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Energy-Quality Scalable Adaptive VLSI Circuits and Systems beyond Approximate Computing,” in Proc. of IEEE DATE 2017 (invited), Lausanne (Switzerland), pp. 127-132, March 2017 (IEEE manuscript, Scholar Bank draft)
R. De Rose, M. Lanuzza, F. Crupi, G. Siracusano, R. Tomasello, G. Finocchio, M. Carpentieri, M. Alioto, “A Variation-Aware Simulation Framework for Hybrid CMOS/Spintronic Circuits,” in Proc. of ISCAS 2017 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Scotti, A. Trifiletti, “Design-Oriented Models for Quick Estimation of Path Delay Variability via the Fan-Out-of-4 Metric,” in print on Proc. of ISCAS 2017 (IEEE manuscript, Scholar Bank draft)
L. Lin, K. Trinh Quang, M. Alioto, “Transistor Sizing Strategy for Simultaneous Energy-Delay Optimization in CMOS Buffers,” in print on Proc. of ISCAS 2017 (IEEE manuscript, Scholar Bank draft)
D. Esposito, A. G. M. Strollo, M. Alioto, “Power-Precision Scalable Latch Memories,” in print on Proc. of ISCAS 2017 (IEEE manuscript, Scholar Bank draft)
S. Jain, M. Alioto, “A Closed-form Energy Model for VLSI Circuits under Wide Voltage Scaling,” in Proc. of ICECS 2016, pp. 548-551, Monaco, Dec. 2016 (IEEE manuscript, Scholar Bank draft)
S. Timarchi, M. Alioto, “Ultra-Low Voltage Standard Cell Libraries: Design Strategies and a Case Study,” in Proc. of ICECS 2016, pp. 520-523, Monaco, Dec. 2016 (IEEE manuscript, Scholar Bank draft)
V. Peluso, A. Calimera, E. Macii, M. Alioto, “Ultra-Fine Grain Vdd-Hopping for Energy-Efficient Multi-Processor SoCs,” in Proc. of VLSI-SoC 2016, pp. 1-6 , Tallinn (Estonia), Sept. 2016 (IEEE manuscript, Scholar Bank draft)
Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, M. Alioto, D. Blaauw, D. Sylvester, “iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2016, pp. 160-161 (IEEE manuscript, Scholar Bank draft)
M. Khayatzadeh, M. Saligane, J. Wang, M. Alioto, D. Blaauw, D. Sylvester, “A Reconfigurable Dual Port Memory with Error Detection and Correction in 28nm FDSOI,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2016, pp. 310-311 (IEEE manuscript, Scholar Bank draft)
K. T. Quang, S. Ruocco, M. Alioto, “Boosted Sensing for Enhanced Read Stability in STTMRAMs,” ISCAS 2016, pp. Montreal (Canada), May 2016 (IEEE manuscript, Scholar Bank draft)
K. T. Quang, S. Ruocco, M. Alioto, “STT-MRAM Write Energy Minimization via Area Optimization Under Dynamic Voltage Scaling,” ISCAS 2016, Montreal (Canada), May 2016 (IEEE manuscript, Scholar Bank draft)
M. Khayatzadeh, F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “A Reconfigurable Sense Amplifier with 3X Offset Reduction in 28nm FDSOI CMOS,” in Proc. of IEEE Symposium on VLSI Circuits, 2015, pp. 5–9 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Comparative Analysis of the Robustness of Master-Slave Flip-Flops Against Variations,” accepted to ICECS 2015, Cairo (Egypt), Dec. 2015 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto, “Better-than-Voltage Scaling Energy Reduction in Approximate SRAMs via Bit Dropping and Bit Reuse,” in Proc. of PATMOS 2015, Salvador (Brazil), Sept 2015 (IEEE manuscript, Scholar Bank draft)
Massimo Alioto, Gaetano Palumbo, Elio Consoli, “PVT Variations in Differential Flip-Flops: A Comparative Analysis,” in Proc. of ECCTD 2015, Trondheim (Norway) (IEEE manuscript, Scholar Bank draft)
Massimo Alioto, Gaetano Palumbo, Elio Consoli, “Variability Budget in Pulsed Flip-Flops,” in Proc. of NEWCAS 2015, Grenoble (France), June 2015 (IEEE manuscript, Scholar Bank draft)
W. Zhao, Y. Ha, M. Alioto, “AES Architectures for Minimum-Energy Operation and Silicon Demonstration in 65nm with Lowest Energy per Encryption,” in Proc. of ISCAS 2015, pp. 2349-2352, Lisbon (Portugal), May 2015 (IEEE manuscript, Scholar Bank draft)
M. Shoaran, A. Tajalli, M. Alioto, Y. Leblebici, “Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators,” in Proc. of ISCAS 2015, pp. 157-160, Lisbon (Portugal), May 2015 (IEEE manuscript, Scholar Bank draft)
K. Trinh Quang, S. Ruocco, M. Alioto, “Modeling the Impact of Dynamic Voltage Scaling on 1T-1J STT-RAM Write Energy and Performance,” in Proc. of ISCAS 2015, pp. 2313-2316, Lisbon (Portugal), May 2015 (IEEE manuscript, Scholar Bank draft)
A. Alvarez, W. Zhao, M. Alioto, “15-fJ/bit Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140X Intra/Inter PUF Hamming Distance Separation in 65nm,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 258-259. (IEEE manuscript, Scholar Bank draft)
M. Alioto, D. Esseni, “Comparative Evaluation of Tunnel-FET Ultra-Low Voltage SRAM Bitcell and Impact of Variations,” in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Analysis and Comparison of Variations in Double Edge Triggered Flip-Flops,” in Proc. of VARI 2014, Palma de Mallorca (Spain), Sept. 2014 (IEEE manuscript, Scholar Bank draft)
M. Alioto, D. Esseni, “Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits,” in proc. of ACM SBCCI 2014, Aracaju (Brazil), Sept. 2014 (IEEE manuscript, Scholar Bank draft)
L. Artola, G. Hubert, M. Alioto, “Comparative SET Evaluation of Layout cells in FinFET Technology,” in print on proc. of ESREF 2014 (IEEE manuscript, Scholar Bank draft)
D. Esseni, M. Alioto, “Device-Circuit Co-Design and Comparison of Ultra-Low Voltage Tunnel-FET and CMOS Digital Circuits,” in proc. of NEWCAS 2014, pp. 321-324, Trois-Riviere (Canada), June 2014 (IEEE manuscript, Scholar Bank draft)
M. Alioto, S. Bongiovanni, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks Against a Bit Slice Implementation of the Serpent Block Cipher,” in print on proc. of MIXDES 2014 (IEEE manuscript, Scholar Bank draft)
F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester, M. Alioto, “A 32kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp. 244-245 (IEEE manuscript, Scholar Bank draft)
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L. Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto, “A 346um2 Reference-Free Sensor Interface for Highly Constrained Microsystems in 28nm CMOS,” in print on proc. of ASSCC 2013, Singapore, Nov. 2013. (IEEE manuscript, Scholar Bank draft)
Y.-P. Chen, Y. Lee, J.-Y. Sim, M. Alioto, D. Blaauw, D. Sylvester, “45pW ESD Clamp Circuit for Ultra-Low Power Applications,” in print on proc. of CICC 2013, San Jose (USA), Sept. 2013. (IEEE manuscript, Scholar Bank draft)
M. Tache, V. Beiu, W. Ibrahim, F. Kharbash, M. Alioto, “Sizing for Static Noise Margins Revisited,” in Proc. of VARI 2013, Karlsruhe (Germany), Sept. 2013. (IEEE manuscript, Scholar Bank draft)
V. Beiu, A. Beg, W. Ibrahim, F. Kharbash, M. Alioto, “Enabling Sizing for Enhancing the Static Noise Margins,” in print on Proc. of ISQED 2013, Santa Clara (California), March 2013. (IEEE manuscript, Scholar Bank draft)
S. Bang, D. Blaauw, D. Sylvester, M. Alioto, “Reconfigurable Sleep Transistor for GIDL Reduction in Ultra-Low Standby Power Systems,” in Proc. of CICC 2012, San Jose, California, Sept. 2012. (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, J. Rabaey, “EChO Power Management Unit with Reconfigurable Switched-Capacitor Converter in 65 nm CMOS,” in Proc. of CICC 2012, San Jose, California, Sept. 2012. (IEEE manuscript, Scholar Bank draft)
J. Richmond, M. John, L. Alarcon, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. R. Sanders, J. M. Rabaey, “Active RFID: A Perpetual Wireless Communications Platform for Sensors,” in print on Proc. of ESSCIRC 2012, Bordeaux (France), Sept. 2012. (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic,” in Proc. of ISCAS 2012, pp. 1576-1579, Seoul (Korea), May 2012. (IEEE manuscript, Scholar Bank draft)
F. Crupi, P. Magnone, M. Alioto, J. Franco, G. Groeseneken, “Early Assessment of Emerging Technologies for VLSI Logic Circuits from Experimental Measurements,” in Proc. of ICSICT 2012 (invited). (IEEE manuscript, Scholar Bank draft)
E. Consoli, M. Alioto, G. Palumbo, J. Rabaey, “Conditional Push-Pull Pulsed Latch with 726 fJ•ps Energy Delay Product in 65nm CMOS,” in Proc. of ISSCC 2012, San Francisco (USA), Feb. 2012. (IEEE manuscript, Scholar Bank draft)
M. Alioto, “’Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells,” in Proc. of ECCTD 2011, pp. 557-561, Linkoping (Sweden), Aug. 2011. (IEEE manuscript, Scholar Bank draft)
F. Frustaci, P. Corsonello, M. Alioto, “Optimization and Evaluation of Tapered-VTH Approach for Energy-Efficient CMOS Buffers,” in print on Proc. of ECCTD 2011, Aug. 2011. (IEEE manuscript, Scholar Bank draft)
F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T. Y. Hoffmann, “Experimental Analysis of Buried SiGe pMOSFETs from the Perspective of Aggressive Voltage Scaling,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (IEEE manuscript, Scholar Bank draft)
D. Baccarin, D. Esseni, M. Alioto, “A Novel Back-Biasing Low-Leakage Technique for FinFET Forced Stacks,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “DET FF Topologies: A Detailed Investigation in the Energy-Delay-Area Domain,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (IEEE manuscript, Scholar Bank draft)
F. Frustaci, P. Corsonello, M. Alioto, “Tapered-VTH CMOS Buffer Design for Improved Energy Efficiency in Deep Nanometer Technology,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (IEEE manuscript, Scholar Bank draft)
M. Djukanovic, L. Giancane, G. Scotti, A. Trifiletti, M. Alioto, “Leakage Power Analysis Attacks: Effectiveness on DPA Resistant Logic Styles under Process Variations,” in print on Proc. of ISCAS 2011, Rio de Janeiro (Brazil), May 2011. (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Nanometer Flip-Flops Design in the E-D Space,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops,” in print on Proc. of ICM 2010, Cairo (Egypt), Dec. 2010. (IEEE manuscript, Scholar Bank draft)
J. Mitard, L. Witters, M. Garcia Bardon, P. Christie, J. Franco, A. Mercha, P. Magnone, M. Alioto, F. Crupi, L.-A. Ragnarsson, A. Hikavyy, B. Vincent, T. Chiarella, R. Loo, J. Tseng, S. Yamaguchi, S. Takeoka, W.-W. Wang, P. Absil, T. Hoffmann, “Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD,” accepted to IEEE IEDM 2010, San Francisco (USA), Dec. 2010. (IEEE manuscript, Scholar Bank draft)
K. Agawa, M. Alioto, W. Zhou, T.-T. Liu, L. Alarcon, K. Hajkazemshirazi, M. John, J. Richmond, W. Li, J. Rabaey, “Design and Verification of an Ultra-Low-Power Active RFID Tag with Multiple Power Domains,” in Proc. of SASIMI2010, Taipei (Taiwan), Oct. 2010. (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits,” in print on Proc. of PATMOS 2010, Grenoble (France), Sept. 2010. (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A Scalable Low-Entropy Detector to Counteract the Parameter Variability effects in TRBGs,” in print on Proc. IMTC 2010, Austin (USA), May 2010. (IEEE manuscript, Scholar Bank draft)
M. Merrett, Y. Wang, M. Alioto, M. Zwolinski, “Design Metrics for RTL Level Estimation of Delay Variability Due to Intradie (Random) Variations,” in Proc. of ISCAS 2010, pp. 2498-2501, Paris (France), May 2010 (IEEE manuscript, Scholar Bank draft)
P. Magnone, F. Crupi, M. Alioto, B. Kaczer, “Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits,” in Proc. of ISCAS 2010, pp. 1699-1702, Paris (France), May 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology,” in Proc. of ISCAS 2010, pp. 3204-3207, Paris (France), May 2010. (IEEE manuscript, Scholar Bank draft)
M. Alioto, P. Bennati, R. Giorgi, “Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed,” in Proc. of ISCAS 2010, pp. 37-40, Paris (France), May 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits,” in Proc. of ISCAS 2010, pp. 1468-1471, Paris (France), May 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Clock Distribution in Clock Domains with Dual-Edge-Triggered Flip-Flops to improve Energy-Efficiency,” in Proc. of ISCAS 2010, pp. 321-324, Paris (France), May 2010 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Optimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study,” in Proc. of ICECS 2009, pp. 275-278, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the Impact of Random Process Variations in CMOS Tapered Buffers,” in Proc. of ICECS 2009, pp. 57-60, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Theoretical Analysis and Impact of Variations,” in Proc. of ICECS 2009, pp. 85-88, Hammamet (Tunisia), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Dependence of Differential Flip-Flops Performance on Clock Slope and Relaxation of Clock Network Design,” in Proc. of ICM 2009, pp. 110-113, Marrakech (Morocco), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, “Low-Overhead Countermeasures to protect Pre-charged Busses against Power Analysis Attacks,” in Proc. of ICM 2009, pp. 159-162, Marrakech (Morocco), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, “Leakage Power Analysis Attacks: Well-Defined Procedure and First Experimental Results,” in Proc. of ICM 2009, pp. 46-49, Marrakech (Morocco), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Analysis and Evaluation of Layout Density of FinFET Logic Gates,” in Proc. of ICM 2009, pp. 106-109, Marrakech (Morocco), Dec. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Impact of Clock Slope on Energy/Delay of Pulsed Flip-Flops and Optimum Clock Domain Design,” in Proc. of ECCTD 2009, pp. 61-64, Antalya (Turkey), Aug. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, M. Pennisi, “Correct Procedures to Evaluate the Effect of Intradie Variations on the Delay Variability of Digital Circuits,” in Proc. of ECCTD 2009, pp. 779-782, Antalya (Turkey), Aug. 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, E. Consoli, G. Palumbo, “Metrics and Design Considerations on the Energy-Delay Tradeoff of Digital Circuits,” in Proc. of ISCAS 2009, pp. 3150-3153, Taipei (Taiwan), May 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, Y. Leblebici, “Analysis and Design of Ultra-Low Power Subthreshold MCML Gates,” in Proc. of ISCAS 2009, pp. 2557-2560, Taipei (Taiwan), May 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “Understanding Loading Effects of RC Uniform Interconnects,” in Proc. of ISCAS 2009, pp. 2269-2272, Taipei (Taiwan), May 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, S. Badel, Y. Leblebici, “Optimization of Wire Grid Size for Differential Routing and Impact on the Power-Delay-Area Tradeoff,” in Proc. of ISCAS 2009, pp. 1285-1288, Taipei (Taiwan), May 2009 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “CAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies,” in Proc. of ICM 2008, pp. 154-157, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, G. Palumbo, “Compact and Simple Output Transition Time Model in Nanometer CMOS Gates,” in Proc. of ICM 2008, pp. 235-238, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, “Power Analysis Attacks to Cryptographic Circuits: a Comparative Analysis of DPA and CPA,” in Proc. of ICM 2008, pp. 308-311, Sharjah (United Arab Emirates), Dec. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, Y. Leblebici, “Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits,” in Proc. of VLSI-SoC 2008, pp. 239-244, Rhodes Island (Greece), Oct. 2008 (INVITED) (IEEE manuscript, Scholar Bank draft)
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici, “Design of High Performance Subthreshold Source-Coupled Logic Circuits,” in Proc. of PATMOS 2008, pp. 21-30, Lisbon (Portugal), Sep. 2008 (IEEE manuscript, Scholar Bank draft)
Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi, “Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction,” in Proc. of PATMOS 2008, pp. 31-41, Lisbon (Portugal), Sep. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic,” in Proc. of PATMOS 2008, pp. 136-145, Lisbon (Portugal), Sep. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Pennisi, “Analysis of the impact of process variations on static logic circuits versus fan-in,” in Proc. of ICECS 2008, pp. 137-140, Malta, Aug. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Energy Evaluation in RLC Tree Circuits with Exponential Input,” in Proc. of ICECS 2008, pp. 578-581, Malta, Aug. 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, L. Fondelli, S. Rocchi, “Analysis and Performance Evaluation of Area-Efficient True Random Bit Generators on FPGAs”, in Proc. of ISCAS 2008, pp. 1572-1575, Seattle (USA), May 2008 (IEEE manuscript, Scholar Bank draft)
A. Tajalli, F. K. Gurkaynak, Y. Leblebici. M. Alioto, E. J. Brauer, “Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage”, in Proc. of ISCAS 2008, pp. 145-148, Seattle (USA), May 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Explicit Energy Evaluation in RLC Tree Circuits with Ramp Inputs”, in Proc. of ISCAS 2008, pp. 2865-2868, Seattle (USA), May 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Power-Delay Optimization in MCML Tapered Buffers”, in Proc. of ISCAS 2008, pp. 141-144, Seattle (USA), May 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, “A General Model for Differential Power Analysis Attacks to Static Logic Circuits”, in Proc. of ISCAS 2008, pp. 3346-3349, Seattle (USA), May 2008 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Efficient and Accurate Models of Output Transition Time in CMOS Logic”, Proc. of ICECS 2007, pp. 1264-1267, Marrakech (Morocco), Dec. 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, “A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic”, Proc. of ICECS 2007, pp. 431-434, Marrakech (Morocco), Dec. 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Energy Consumption in RLC Tree Circuits”, Proc. of ECCTD 2007, pp. 771-774, Sevilla (Spain), Aug. 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Very High-Speed Carry Computation based on Mixed Dynamic/Transmission-Gate Full Adders”, Proc. of ECCTD 2007, pp. 799-802, Sevilla (Spain), Aug. 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms”, Proc. of ECCTD 2007, pp. 368-371, Sevilla (Spain), Aug. 2007 (IEEE manuscript, Scholar Bank draft)
M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, “Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs”, Proc. of ESSDERC 2007, pp. 191-194, Munich (Germany), Sept. 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Delay Variability Due to Supply Variations in Transmission-Gate Full Adders”, Proc. of ISCAS 2007, pp. 3732-3735, New Orleans (USA), May 2007 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Maximum-Period PRBGs Derived From A Piecewise Linear One-Dimensional Map”, Proc. of ISCAS 2007, pp. 693-696, New Orleans (USA), May 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology”, Proc. of ISCAS 2007, pp. 2998-3001, New Orleans (USA), May 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects”, Proc. of SCAS 2007, pp. 3255-3258, New Orleans (USA), May 2007 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Mixed Techniques to Protect Precharged Busses against Differential Power Analisys Attacks”, Proc. of ISCAS 2007, pp. 861-864, New Orleans (USA), May 2007 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, “Implementation-Efficient Maximum-Period Nonlinear Congruential Generators”, Proc. of IMTC 2007, Warsaw (Poland), May. 2007 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Efficient Post-Processing Module for a Chaos-based Random Bit Generator”, Proc. of ICECS2006, pp. 1224-1227, Nice (France), Dec. 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Modeling of Delay Variability due to Supply Variations in Pass-Transistor and Static Full Adders”, Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, R. Mita, G. Palumbo, “A Design Methodology for High-Speed Low-Power MCML Frequency Dividers”, Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Entropy Enhancement in a Chaos-Based True Random Bit Generators”, Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis”, Proc. of PATMOS 2006, pp. 624-633, Montpellier (France), Sept. 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, M. Poli, S. Rocchi, V. Vignoli, “Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm”, Proc. of PATMOS 2006, pp. 593-602, Montpellier (France), Sept. 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, A. D. Grasso, G. Palumbo, “Design of Cascaded ECL Gates with a Power Constraint”, Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “A Technique to Design High Entropy Chaos-Based True Random Bit Generators”, Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, M. Poli, “Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs”, Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, “Analysis and Design of MCML Gates with Hysteresis”, Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Nanometer MCML Gates: Models and Design Considerations”, Proc. of ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006 (IEEE manuscript, Scholar Bank draft)
M. Alioto, G. Palumbo, “Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders”, Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006 (IEEE manuscript, Scholar Bank draft)
T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, “Uniform-Distributed Noise Generator Based on a Chaotic Circuit”, Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006 (IEEE manuscript, Scholar Bank draft)Trends in Hardware Security: from Basics to ASICs