ISSCC 2014 paper in collaboration with University of Michigan, Ann Arbor

Collaboration with Prof. David Blaauw and Prof. Dennis Sylvester (Umich) led to the work that we presented at ISSCC 2014.Our 28-nm chip demonstrates the absolutely first SRAM that can flexibly operate in error-free (traditional) or error-tolerant (errors occur, although in a controlled way) mode with dynamic and wide adjustment of the energy-quality tradeoff. This is […]

IEEE TVLSI paper on the fastest/most energy efficient pulsed latch just accepted (in collaboration with BWRC-UCBerkeley)

Collaboration with Prof. Jan Rabaey (UCBerkeley) led to a new paper that will be published on the IEEE Transactions on VLSI Systems. To probe further: E. Consoli, G. Palumbo, J. Rabaey, M. Alioto, “A Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches,” in print on IEEE Trans. on VLSI Systems. Abstract: In this paper, […]

JSSC paper in collaboration with BWRC-UCBerkeley just accepted

Collaboration with Prof. Jan Rabaey (UCBerkeley) leads to a new paper that will be published on the IEEE Journal of Solid-State Circuits on the August special issue. To probe further: Massimo Alioto, Elio Consoli, Jan Rabaey, ““EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions,” in print on JSSC, Aug. 2013. Abstract: A novel reconfigurable switched-capacitor […]